共查询到20条相似文献,搜索用时 15 毫秒
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I. Grech J. Micallef C. J. Debono P. Malcovati F. Maloberti 《Analog Integrated Circuits and Signal Processing》2001,27(1-2):151-163
A second order switched capacitor sigma-delta modulator operating at a supplyvoltage of 1 V is presented. This low supply voltage restricts the gate overdrivevoltage available for switching transistors. The design relies on the elimination ofcritical switches by using a modified switched op amp for the integrator and novelswitched half-supply and reference voltage generators. The design has been carried outin a fully differential configuration in order to minimize errors arising from chargeinjection and clock-feedthrough effects. The converter has been implemented using aconventional 0.8 m double-poly double-metal CMOS process, having a nominalthreshold voltage of 0.75 V. Test results, showing more than 9 bits of resolutionwith an oversampling ratio of 64, are also presented. 相似文献
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介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度ΣΔ调制器. 为了达到高线性和稳定性,调制器采用2-1级联单比特的结构实现. 电路在0.18μm CMOS工艺下流片验证,核心面积为0.5mm×1.1mm. 调制器工作在19.2MHz的采样频率,在3V电源电压下功耗为5.88mW. 测试结果表明,在200kHz信号带宽,过采样率为64的条件下,调制器达到84.4dB动态范围,峰值SNDR达到73.8dB,峰值SNR达到80dB. 相似文献
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介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度∑△调制器.为了达到高线性和稳定性,调制器采用2-1级联单比特的结构实现.电路在0.18μm CMOS工艺下流片验证,核心面积为0.5mm×1.1mm.调制器工作在19.2MHz的采样频率,在3V电源电压下功耗为5.88mW.测试结果表明,在200kHz信号带宽,过采样率为64的条件下,调制器达到84.4dB动态范围,峰值SNDR达到73.8dB,峰值SNR达到80dB. 相似文献
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Michio Yotsuyanagi Hiroshi Hasegawa Masaharu Satoh 《Analog Integrated Circuits and Signal Processing》2000,25(3):227-234
A 1.5 V 8 mW BiCMOS video A/D converter has been developed by using a BiCMOS pumping comparator. Combining Bipolar high-speed and good-matching characteristics with CMOS switched capacitor techniques, this A/D converter is suitable for use in battery-operated multimedia terminals. 相似文献
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P. Benabes A. Gauthier R. Kielbasa 《Analog Integrated Circuits and Signal Processing》1996,11(3):195-204
A new family of high order Sigma Delta modulators called MSCL (Multi Stage Closed-loop) is presented in this paper. They use a global feedback to lower the sensitivity to circuit imperfections. This feedback from the output of the modulator is the sum of the output of each comparator so that no digital prefiltering is required before summing up these signals. However, easy calibration will be required to compensate for the feedback imperfections.MSCL modulators present the same insensitivity to circuit imperfections as classical multi-order one-bit converters, but reach the performance of high-order MASH (MultistAge noise SHaping) modulators. They help make high-order low-pass or band-pass modulators without limit cycles so that their quantizing noise characteristics are similar to those predicted by the linear simplified model. 相似文献
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Σ-Δ模拟/数字转换器综述 总被引:1,自引:1,他引:0
Σ-ΔA/D转换器是利用速度换取精度的高精度模拟/数字转换器。文章分析了Σ-ΔA/D转换器的产生、组成和优势,重点介绍了Σ-Δ调制器结构及其性能指标,简要介绍了数字抽取滤波器。对Σ-ΔA/D转换器国内外发展状况进行了全面的分析。在此基础上,论述了Σ-ΔA/D转换器未来的发展趋势。 相似文献
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Geir S. Østrem Øystein Moldsvor Oddvar Aaserud 《Analog Integrated Circuits and Signal Processing》1998,15(1):27-36
A 12-bit video speed pipelined switched capacitor analog-to-digitalconverter (ADC) has been implemented in a 0.5 µmstandard CMOS process. It operates from a single 2.6–;3.3Vsupply, dissipates 23mA (independent of supply voltage) at 20MSPS and occupies only 1.1mm 2. A 61dB SINAD (fin = 4.5 MHz) and an effective resolution bandwidthof 9 MHz is achieved. 相似文献
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本文描述了一种14位20Msps模数转换器的设计,该器件基于0.18μm CMOS 工艺,能在奈奎斯特率下实现了11.2有效位。通过无采样保持放大器(SHA-less)结构和运放共享技术使功耗大大降低。提出的一种快速后台校准有效保证了整体的线性度。在1.8V电源电压下,该模数转换器功耗仅为166mW. 相似文献
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本文提出一个采用三阶滤波器,三位量化器的连续时间ΔΣ 调制器。该调制器对环路延迟,时钟抖动,以及RC时间常数变化具有鲁棒性。在积分器设计中,采用了增益带宽积扩展结构的运放,提高了滤波器的线性度。该芯片使用130nmCMOS工艺设计,可以应用在调频接收机中。测试结果表明,在带宽为500 kHz,时钟为26MHz条件下,该调制器实现了72dB的动态范围和70.7dB的信噪失真比,在1.2V电压下消耗2.52mW功耗。 相似文献
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Yonghong Gao Lihong Jia Jouni Isoaho Hannu Tenhunen 《Analog Integrated Circuits and Signal Processing》2000,22(1):51-60
This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz. 相似文献
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本文设计了一种可满足视频速度应用的低电压低功耗10位流水线结构的CMOS A/D转换器.该转换器由9个低功耗运算放大器和19个比较器组成,采用1.5位/级共9级流水线结构,级间增益为2并带有数字校正逻辑.为了提高其抗噪声能力及降低二阶谐波失真,该A/D转换器采用了全差分结构.全芯片模拟结果表明,在3V工作电压下,以20MHz的速度对2MHz的输入信号进行采样时,其信噪失调比达到53dB,功率消耗为28.7mW.最后,基于0.6μm CMOS工艺得到该A/D转换器核的芯片面积为1.55mm2. 相似文献
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设计了应用于GMSK调制,工作在2.4GHz,CMOS全差分的∑-△频率综合器.调制器中采用预补偿的分数N锁相环.推导了Ⅱ型三阶锁相环的传输函数,并指出影响环路传输函数的重要参数.介绍了校准重要的环路参数的方法.锁相环设计中采用差分调节的LC压控振荡器和全差分的电荷泵.设计的电路利用0.18μm 1P6M CMOS工艺进行仿真.由于锁相环的组成模块中采用了低功耗设计,锁相环的功耗仅为11mW左右,调制器的数据率达到2Mb/s. 相似文献
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设计了应用于GMSK调制,工作在2.4GHz,CMOS全差分的∑-△频率综合器.调制器中采用预补偿的分数N锁相环.推导了Ⅱ型三阶锁相环的传输函数,并指出影响环路传输函数的重要参数.介绍了校准重要的环路参数的方法.锁相环设计中采用差分调节的LC压控振荡器和全差分的电荷泵.设计的电路利用0.18μm 1P6M CMOS工艺进行仿真.由于锁相环的组成模块中采用了低功耗设计,锁相环的功耗仅为11mW左右,调制器的数据率达到2Mb/s. 相似文献