三维集成封装中的TSV互连工艺研究进展

为顺应摩尔定律的增长趋势,芯片技术已来到超越"摩尔定律"的三维集成时代。电子系统进一步小型化和性能提高,越来越需要使用三维集成方案,在此需求推动下,穿透硅通孔(TSV)互连技术应运而生,成为三维集成和晶圆级封装的关键技术之一。TSV集成与传统组装方式相比较,具有独特的优势,如减少互连长度、提高电性能并为异质集成提供了更宽的选择范围。三维集成技术可使诸如RF器件、存储器、逻辑器件和MEMS等难以兼容的多个系列元器件集成到一个系统里面。文章结合近两年的国外文献,总结了用于三维集成封装的TSV的互连技术和工艺,探讨了其未来发展方向。     

用于3D集成中的晶圆和芯片键合技术

3D集成技术包括晶圆级、芯片与晶圆、芯片与芯片工艺流程,通过器件的垂直堆叠得到其性能的提升,并不依赖于基板的尺寸和技术。所有的报道均是传输速度提高,功耗降低,性能更好及更小的外形因素等优势使得这种技术的名气大振。选择晶圆或芯片级集成的决定应基于几个关键因素的考虑。对于不同种类CMOS、非CMOS器件间的集成,芯片尺寸不匹配引发了衬底的变化(如300mm对150mm).芯片与晶圆或芯片与芯片的堆叠也许是唯一的选择。另外,当芯片的成品率明显地不同于晶圆与晶圆键合方法时,在堆叠的晶圆中难以使确认好芯片的量达到最大。在这种情况下,应将一枚或两枚晶圆划切成小芯片并仅将合格的芯片垂直地集成。只要适当地采用晶圆与晶圆键合工艺便可实现高成品率器件同类集成。晶圆间键合具有最高的生产效率,工艺流程简便及最小的成本。满足选择晶圆级或芯片级工艺总的工艺解决方案应结合对准和键合细节来考虑决定最终的设备选择和工艺特性。所有这些工艺的论证证实对于多数产品的制造3D集成是可行的,而且有些也已成为生产的主流。     

Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

Thermal stress issues in a three-dimensional (3D) stacked wafer system were examined using finite-element analysis of the stacked wafers. This paper elucidates the effects of the bonding dimensions on mechanical failure and the keep-away zone, where devices cannot be located because of the stress in the Si. The key factors in decreasing the thermal strain were the bonding diameter and thickness. When the bonding diameter decreased from 40 μm to 12 μm, the equivalent strain decreased by 83%. It is noteworthy that the keep-away zone also decreased from 17 μm to zero when the bonding diameter decreased from 40 μm to 12 μm. When the bonding thickness doubled, the equivalent strain decreased by 44%. The effects of the dimensions and arrangement of through-silicon vias (TSV) were also analyzed. Small TSV diameter and pitch are important to decrease the equivalent strain, especially when the amount of Cu per unit volume is fixed. When the TSV diameter and pitch decreased fourfold, the equivalent strain decreased by 70%. The effects of TSV height and the number of die stacks were not significant, because the underfill acted as a buffer against thermal strain.     

应用于3D集成的高密度Cu/Sn微凸点键合技术

3D-IC技术被看作是应对未来半导体产业不断增长的晶体管密度最有希望的解决方案,而微凸点键合技术是实现3D集成的关键技术之一.采用电镀工艺制作了直径为50μm、间距为130μm的高密度Cu/Sn微凸点,分析了不同预镀时间及电流密度对Cu微凸点形成质量的影响,并使用倒装焊机实现了高密度Cu/Sn微凸点的键合.利用直射式X射线、分层式X射线对键合样片进行无损检测,结果表明键合对准精度高,少量微凸点边缘有锡被挤出,这是由于锡层过厚导致.观察键合面形貌,可以发现Cu和Sn结合得不够紧密.进一步对键合面金属间化合物进行能谱分析,证实存在Cu6 Sn5和Cu3 Sn两种物质,说明Cu6 Sn5没有与Cu充分反应生成稳态产物Cu3 Sn,可以通过增加键合时间、减少Sn层厚度或增加退火工艺来促进Cu3 Sn的生成.     

Ultrasonic Bonding Using Anisotropic Conductive Films (ACFs) for Flip Chip Interconnection

In this paper, a novel anisotropic conductive film (ACF) flip chip bonding method using ultrasonic vibration for flip chip interconnection is demonstrated. The curing and bonding behaviors of ACFs by ultrasonic vibration were investigated using a 40-kHz ultrasonic bonder with longitudinal vibration. In situ temperature of the ACF layer during ultrasonic (U/S) bonding was measured to investigate the effects of substrate materials and substrate temperature. Curing of the ACFs by ultrasonic vibration was investigated by dynamic scanning calorimetry (DSC) analysis in comparison with isothermal curing. Die adhesion strength of U/S-bonded specimens was compared with that of thermo-compression (T/C) bonded specimens. The temperature of the ACF layer during U/S bonding was significantly affected by the type of substrate materials rather than by the substrate heating temperature. With room the temperature U/S bonding process, the temperature of the ACF layer increased up to 300degC within 2 s on FR-4 substrates and 250degC within 4 s on glass substrates. ACFs were fully cured within 3 s by ultrasonic vibration, because the ACF temperature exceeded 300degC within 3 s. Die adhesion strengths of U/S-bonded specimens were as high as those of T/C bonded specimens both on FR-4 and glass substrates. In summary, U/S bonding of ACF significantly reduces the ACF bonding times to several seconds, and also makes bonding possible at room temperature compared with T/C bonding which requires tens of seconds for bonding time and a bonding temperature of more than 180degC.     

Analysis of 3D TSV Vertical Interconnection Using Pre-applied Nonconductive Films

Much research has been carried out to realize through-silicon via (TSV) technology for three-dimensional (3D) chip stacking packaging. A vertical chip interconnection method using Cu/Sn-Ag bumps and nonconductive films (NCFs) is one of the most promising approaches for 3D TSV vertical interconnection. In this work, the relationship between the viscosity of pre-applied NCFs and loading forces was investigated to predict the gap change between a TSV chip and a substrate chip. Existing theories of squeeze flow are adapted to predict the gap change of a real TSV chip and a substrate chip during TSV bonding using a simplified model. The real gaps measured during bonding of test dies were matched to check the validity of the prediction model. Considering the thixotropy of NCFs, the prediction well matched the real gap changes between bumped TSV chips and substrate chips during bonding.     

Investigation and Effects of Wafer Bow in 3D Integration Bonding Schemes

This paper investigates and reviews the effects of wafer bow in three-dimensional (3D) integration bonding schemes, including copper wafer bonding and oxide fusion wafer bonding with silicon on insulator (SOI)-based layer transfer technology. Wafer bow criteria for good bonding quality and fabrication techniques to minimize wafer bow are introduced for 3D integration technology and applications.     

应用于三维集成的晶圆级键合技术

随着芯片集成度的不断提高以及CMOS工艺复杂度的增加,集成电路的成本及性能方面的问题越来越突出,基于TSV技术的三维集成已成为研究热点,并很有可能是未来集成电路发展的方向.在三维集成中,键合技术为芯片堆叠提供电学连接和机械支撑,从而实现两层或多层芯片间电路的垂直互连.介绍了几种晶圆级三维集成键合技术的特点及研究现状.     

3D集成晶圆键合装备现状及研究进展

硅基异构集成和三维集成可满足电子系统小型化高密度集成、多功能高性能集成、小体积低成本集成的需求,有望成为下一代集成电路的使能技术,是集成电路领域当前和今后新的研究热点.硅基三维集成微系统可集成化合物半导体、CMOS、MEMS等芯片,充分发挥不同材料、器件和结构的优势,可实现传统组件电路的芯片化、不同节点逻辑集成电路芯片...     

Modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias

Through-silicon via(TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits(3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-frequency applications. In this paper, a rigorous analytical inductance model of 3D solenoid inductor is proposed based on the concept of loop and partial inductance. And a series of 3D samples are fabricated on 12-in high-resistivity silicon wafer using low-cost standard CMOS-compatible ...     

三维集成

在封装的舞台上,三维集成技术因为在提高电子系统的性能和微型化方面效果卓著而引起重视。目前三维技术的手段一般采用较长的焊线来连接堆叠芯片和基层。新的三维概念仍处在开发阶段,但它将提供更短的互联,更高的互联密度,更低的成本。对于不同的应用,需要有相应且适宜的3D技术。     

一种三维芯片间的低功耗单相位调制收发电路

基于三维堆叠芯片间电感耦合无线互联的方法,设计了一种用于三维芯片间的低功耗单相位调制收发电路。相比于传统的双相位调制收发电路,单相位调制收发电路能将功耗降低58%,而且不牺牲收发电路的其他性能。采用新芯XMC 65 nm CMOS工艺进行设计,电源电压为1.2 V,收发电路的工作速度可达1 Gb/s,功耗仅为1.25 mW,误码率小于1×10-13。单相位调制传输方式能够很好地运用于三维芯片间电感耦合互联的低功耗应用领域。     

面向三维集成应用的Cu/SiO2晶圆级混合键合技术研究进展

Cu/SiO₂混合键合技术被认为是实现芯片三维集成和高密度电学互连的理想方案,但由于其需兼顾介质和金属两种材料的键合,目前鲜有自主开发且工艺简单、成本低廉的混合键合方案的报道。文章归纳了现有的晶圆级键合技术,包括直接键合、活化键合以及金属固液互扩散键合,分析了其应用于混合键合技术的可能性。进一步总结了近年来部分Cu/SiO₂混合键合技术的研究进展,从原理上剖析该工艺得以实现的关键,为国内半导体行业占领此高端领域提供一定的参考。     

三维微波多芯片组件垂直微波互联技术

三维微波多芯片组件是新一代固态有源相控阵共形天线和智能蒙皮的核心部件。文章详细介绍了实现三维微波多芯片组件最关键的小型化、低插入损耗和高可靠的垂直微波互联技术,对采用毛纽扣结构的无焊接垂直微波互联和采用环氧树脂包封的垂直微波互联、微波传输结构进行了仿真和优化,研发出相应的制作工艺,实现了三维微波多芯片组件微小型化、大工作带宽、低插入损耗和高可靠垂直微波互联。     

3D堆叠芯片硅通孔的电-热-力耦合构形设计

建立了3D堆叠芯片硅通孔(TSV)单元体模型,在单元体总体积和TSV体积占比给定时,考虑电-热-力耦合效应,以最高温度、(火积)耗散率、最大应力和最大形变为性能指标,对TSV横截面长宽比和单元体横截面长宽比进行双自由度构形设计优化.结果表明,存在最佳的TSV横截面长宽比使得单元体的最高温度、(火积)耗散率和最大应力取得极小值,但对应不同优化目标的最优构形各有不同,且TSV两端电压和芯片发热功率越大,其横截面长宽比对各性能指标的影响越大.铜、铝、钨3种材料中,钨填充TSV的热学和力学性能最优,但其电阻率较大.铜填充时,4个指标中最大应力最敏感,优先考虑最大应力最小化设计需求以确定TSV几何参数,可以较好兼顾其他性能指标.     

Novel Maskless Bumping for 3D Integration

A novel, maskless, low‐volume bumping material, called solder bump maker, which is composed of a resin and low‐melting‐point solder powder, has been developed. The resin features no distinct chemical reactions preventing the rheological coalescence of the solder, a deoxidation of the oxide layer on the solder powder for wetting on the pad at the solder melting point, and no major weight loss caused by out‐gassing. With these characteristics, the solder was successfully wetted onto a metal pad and formed a uniform solder bump array with pitches of 120 µm and 150 µm.     

Effects of Bonding Temperature and Pressure on the Electrical Resistance of Cu/Sn/Cu Joints for 3D Integration Applications

This study reports the effects of bonding conditions (temperature and pressure) on the bonding morphology and electrical resistance of a Cu/Sn/Cu structure. By carefully characterizing the bond using several analytical methods [scanning electron microscopy (SEM), electron probe microanalysis (EPMA), and transmission electron microscopy (TEM)], we have learned that bonding the samples under various conditions produces greatly different bond morphologies, as well as different prevailing phases in the bonded layer. However, measurements of the electrical resistance of the joints reveal a relative insensitivity to the bonding conditions, signaling that the microstructural evolution and the bond morphology do not strongly influence the resistance.     

柔性聚合物基材上三维纳米问隙的制作及互连

利用普通的紫外光刻、等离子体刻蚀、剥离和薄膜技术,在生物和半导体技术兼容的柔性聚对二甲苯-C基材上制作出了三维纳米间隙结构.室温下,使用介质电泳的方法对制作的纳米间隙进行材料集成实验.在间距80 nm的间隙电极间,实现了碳纳米管的互连.Ⅰ-Ⅴ特性测试显示,互联后电极之间表现出了较好的线性导电特征.当使用的碳纳米管电泳液...     

Using Transmission Laser Bonding Technique for Line Bonding in Microsystem Packaging

The transmission laser bonding (TLB) technique has been developed for the formation of continuous line bonds for microsystem packaging applications. Line bonds are generated by overlapping single bonding spots, in which the degree of overlapping is achieved by varying the scanning speed of the laser as it irradiates the bonding wafers. An analytical model has been developed to guide the TLB process, attaining a uniform laser intensity that produces uniform bonds, satisfying the bonding requirements. Guided by this model, experiments have been conducted to bond Pyrex glass-to-Si wafers at various bonding conditions. To demonstrate the reliability of the technique and the model developed, the strength of the resulting bonded pairs has been evaluated by a micro tensile tester. At contact pressures higher than 1 MPa, the strength of bonded lines can reach a stable value of 9.2 MPa, which is comparable to those obtained by other major bonding processes. To further understand the associated bonding mechanism, the bonded interface has also been analyzed using auger electron spectroscopy and X-ray photoelectron spectroscopy, quantifying the drifting or diffusion of atoms that occurs between glass and Si wafers during the bonding process