Investigation of programming charge distribution in nonoverlapped implantation nMOSFETs

Novel gate-to-drain nonoverlapped-implantation (NOI) nMOSFETs have been developed as potential multibit-per-cell nonvolatile-memory (NVM) devices. The lateral charge distribution of the NOI NVM device programmed by channel hot electron injection is investigated by charge-pumping (CP) techniques with presumed interface trap distributions. For the first time, the CP results have revealed the lateral charge distribution and trapping density at the NOI's programmed state. The maximum trapping charge density locates near its drain junction. The charge distribution is estimated about 90 nm in length and spread widely over the NOI region. Two-dimensional simulators with charge bars using the same charge trapping distribution confirm the experimental results by fitting their I/sub DS/-V/sub G/ curves.     

A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

New investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.     

Refinement of Unified Random Access Memory

This paper investigates how gate height $(H_{g})$, which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a 1T-DRAM operation. A device with a lower $H_{g}$ yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower $H_{g}$ shows slightly poor retention characteristics in the NVM unlike the 1T-DRAM.      

Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance

We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-gate voltage (V_cg) and nonvolatile memory (NVM) function. The additional NVM function is achieved by Fowler-Nordheim (FN) tunneling electron injection into the nitride storage node. The injected electrons induce a permanent hole accumulation layer in silicon body which improves the sensing margin and retention time characteristics. To demonstrate the effect of stored electrons in the nitride layer, experimental data are provided using 0.6 μm devices fabricated on SOI wafers.     

非挥发性记忆体Read Disturb测试方法的研究

DDF是一种高容量的NAND Flash。以DDF产品为例,研究和讨论了它的Read Disturb测试方法。受测试时间的限制,只能选择局部的存储区间进行DDF的Read Disturb测试。这样局部区间的测试结果是否能够代表整个芯片的性能,设计了一套实验,对这个课题进行了研究和讨论。依据非挥发性记忆体产品的特性,主要以阈值电压的分布为参考来评价DDF芯片性能的一致性和性能恶化趋势的一致度。最后的实验结果证明了这种测试方法的正确性和合理性。这种分析方法也可以用于其他非挥发性记忆体产品的其他可靠性测试项目的评估。     

Metal nanocrystal memory with high-/spl kappa/ tunneling barrier for improved data retention

A nonvolatile memory (NVM) with metal nanocrystal (NC) embedded in high-/spl kappa/ dielectrics is proposed. With the larger work function of the metal NC compared to that of silicon NC, the metal NC memory exhibits the better data retention characteristic. The theoretical analysis showing the effect of the electron barrier height on tunneling current density is also presented to support the importance of work function engineering of the NC in NVM structure. The other electrical characteristics such as the programming transient and data endurance are also studied and described in this paper.     

A revew of in situ transmission electron microscopy study on the switching mechanism and packaging reliability in non-volatile memory

Non-volatile memory(NVM)devices with non-volatility and low power consumption properties are important in the data storage field.The switching mechanism and packaging reliability issues in NVMs are of great research interest.The switch-ing process in NVM devices accompanied by the evolution of microstructure and composition is fast and subtle.Transmission electron microscopy(TEM)with high spatial resolution and versatile external fields is widely used in analyzing the evolution of morphology,structures and chemical compositions at atomic scale.The various external stimuli,such as thermal,electrical,mechanical,optical and magnetic fields,provide a platform to probe and engineer NVM devices inside TEM in real-time.Such ad-vanced technologies make it possible for an in situ and interactive manipulation of NVM devices without sacrificing the resolu-tion.This technology facilitates the exploration of the intrinsic structure-switching mechanism of NVMs and the reliability is-sues in the memory package.In this review,the evolution of the functional layers in NVM devices characterized by the ad-vanced in situTEM technology is introduced,with intermetallic compounds forming and degradation process investigated.The principles and challenges of TEM technology on NVM device study are also discussed.     

高k介质在浮栅型非挥发性存储器中的应用

随着微电子技术节点不断向前推进,基于传统浮栅结构的非挥发性存储器(NVM)技术遇到严重的技术难点,其中最主要的问题是SiO2隧穿层已经接近厚度极限,很难继续减薄.作为改进措施,引入高k介质作为新型隧穿层材料.文章介绍了高k材料的研究现状和在NVM器件中应用所取得的进展;最后,对高k介质进一步应用的研究趋势进行了展望.     

Indium-tin-oxide,free, flexible,nonvolatile memory devices based on graphene quantum dots sandwiched between polymethylsilsesquioxane layers

Indium-tin-oxide (ITO) free, nonvolatile memory (NVM) devices based on graphene quantum dots (GQDs) sandwiched between polymethylsilsesquioxane (PMSSQ) layers were fabricated directly on polyethylene terephthalate (PET) substrates by using a solution process technique. Current-voltage (I-V) curves for the silver nanowire/PMSSQ/GQD/PMSSQ/poly(3,4-ethylenethiophene):poly(styrene sulfonate)/PET devices at 300 K showed a current bistability. The ON/OFF ratio of the current bistability for the NVM devices was as large as 1 × 10⁴, and the cycling endurance time of the ON/OFF switching for the NVM devices was above 1 × 10⁴ s. The Schottky emission, Poole-Frenkel emission, trapped-charge limited-current, and space-charge-limited current were dominantly attributed to the conduction mechanisms for the fabricated NVM devices based on the obtained I-V characteristics, and energy band diagrams illustrating the “writing” and the “erasing” processes of the devices.     

Personal communications services: the next technological revolution

The US Federal Communications Commission (FCC) has issued a Notice of Inquiry (NOI) to consider whether to allocate frequencies for personal communications services (PCS), the particular PCS offerings to authorize, the technical standards that licensees should follow, and the regulatory policies tha should govern PCS operations, including who may be eligible for PCS licenses. An overview is given of the reaction that the NOI has generated and the critical threshold decisions that the FCC will be making. These are discussed in the context of the need for PCS spectrum allocation and industry structure issues     

Disk Triboelectric Nanogenerator-Based Nonvolatile Memory toward Smart Identification System

With the rapid advancement of the Internet of things (IoT), security issues of the IoT are emerging because the wireless networks for conventional IoT are easily exposed to hacking. By storing the critical data in a physically separate space, these issues can be suppressed. The nonvolatile memory (NVM) is an attractive solution because the stored data are not erased even after turning off the power. However, the NVM consumes the power for operating and remaining data are exposed to attack. Hence, NVM with high security and low power operation is highly required for IoT platforms. Herein, a disk triboelectric nanogenerator-based NVM (DTNVM) is developed. The DTNVM can be operated with low power because the reading process of stored data is conducted with triboelectricity. Since the ternary system is adopted, 23 to 119 trits can be stored at the DTNVM by changing the sampling time. The identification information is stored at the DTNVM and 91.3% of consistency of the data with a range of 10% tolerance is recorded as result of the reading. Based on the result, the DTNVM is expected to be utilized in the near future as a next-generation NVM and for safe identification systems at the IoT.     

Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

Operation properties of polysilicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile semiconductor memory (NVM) devices with stacked tunneling and charge trapping layers were investigated in this work. Clear enhancement on operation speed and satisfactory retention of NVM device were achieved by adopting stacked tunneling oxide. Enhancement on programming speed but degradation on erasing operation was observed for device with stacked charge trapping layer. Finally, operating characteristics of devices with stacked tunneling oxide, stacked charge trapping layer, and combining both stacked tunneling oxide and charge trapping layer were compared and discussed.     

Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory

Non-volatile memories (NVMs) show great potential in replacing DRAM as the main memory in many embedded systems because of their attractive characteristics such as low cost, high density, and low energy consumption. However, the problem of asymmetric read and write costs has to be addressed before the advantages of NVM can be fully exploited. That is, the cost of write operation is much more expensive than the cost of read operation on NVMs. The existing techniques for loop optimization cannot be used effectively with non-volatile main memory because this special feature is not considered. In this paper, we propose an efficient loop scheduling algorithm, the Rotation with Maximum Bipartite Matching (RMBM) algorithm, to address the problem of expensive write operations on non-volatile main memory for chip multiprocessors (CMPs). It achieves high parallelism for a loop and, at the same time, reduces the number of write operations on NVM. The experimental results show that the RMBM algorithm reduces the number of write activities on NVM by 34.5 % on average compared with the traditional rotation scheduling algorithm. The execution time is reduced by 20.5 %, and the energy consumption is also reduced by 15.03 % on average using the RMBM algorithm. In other words, the average lifetime of NVM can be extended by more than 2 times using the proposed technique.     

内嵌式逻辑型非挥发性内存技术与应用

内嵌式非挥发性内存,具备高良率、高精准度与配合系统做参数调效的特性,能使整体系统具最短开发时程与生产成本。内嵌式非挥发性内存的发展可分为传统型与逻辑型。传统型内嵌式非挥发性内存的制造过程相当复杂,相对于一般逻辑制程来说,需额外增加7-9道光罩。逻辑型非挥发性存储器则不同于传统型,其利用一般逻辑制程中之I／O组件来组成非挥发性内存之核心存储单元。基于技术成熟度与生产成本因素,逻辑型非挥发性内存成为在逻辑制程中使用度最高之解决方案。其可应用之范围包含所有使用兼容于一般逻辑制程的数字／模拟芯片。未来逻辑型非挥发性内存解决方案会成为一标准化设计,并被广泛使用于各类消费型电子产品中。     

A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure

A novel 2-bit/cell nonvolatile memory (NVM) with metal-oxide-nitride-oxide-semiconductor (MONOS) asymmetric double gate (ADG) MOSFET structure is proposed. With the double gate structure, the two conducting channels provide the ability to store 2 bits in a cell. Program and erase can be performed by channel hot electron (CHE) injection and Fowler-Nordheim (FN) tunneling respectively. The read operation and the array structure of the proposed novel NVM are also studied and described in this paper.     

Utilization-Aware Data Variable Allocation on NVM-Based SPM in Real-Time Embedded Systems

With the development of the nonvolatile memory (NVM), using NVM in the design of the cache and scratchpad memory (SPM) has been increased. This paper presents a...     

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition. The battery life is the critical problem for wearable devices. The non-volatile memory (NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption, NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory (DRAM). In this paper, we assume to use hybrid random access memory (RAM) and NVM architecture for the smart bracelet system. This paper presents a data management algorithm named bracelet power-aware data management (BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.     

基于新型非易失存储器的混合内存架构的内存管理机制

随着互联网和云计算技术的迅猛发展,现有动态随机存储器（Dynamic Random Access Memory,DRAM）已无法满足一些实时系统对性能、能耗的需求.新型非易失存储器（Non-Volatile Memory,NVM）的出现为计算机存储体系的发展带来了新的契机.本文针对NVM和DRAM混合内存系统架构,提出一种高效的混合内存页面管理机制.该机制针对内存介质写特性的不同,将具有不同访问特征的数据页保存在合适的内存空间中,以减少系统的迁移操作次数,从而提升系统性能.同时该机制使用一种两路链表使得NVM介质的写操作分布更加均匀,以提升使用寿命.最后,本文在Linux内核中对所提机制进行仿真实验.并与现有内存管理机制进行对比,实验结果证明了所提方法的有效性.     

A novel 2-T structure memory device using a Si nanodot for embedded application

Performance and reliability of a 2 transistor Si nanocrystal nonvolatile memory(NVM) are investigated. A good performance of the memory cell has been achieved,including a fast program/erase(P/E) speed under low voltages,an excellent data retention(maintaining for 10 years) and good endurance with a less threshold voltage shift of less than 10%after 10~4 P/E cycles.The data show that the device has strong potential for future embedded NVM applications.     

Functional modelling of non-volatile MOS memory devices

A simple first-order model of semiconductor non-volatile memory (NVM) devices is formulated. Conduction through the dielectric layers is as usual described by a dielectric resistivity, ρ but unlike the usual models which describe ρ by theoretical expressions, we have chosen to obtain ρ from experimental data on MIS capacitors. It turns out that the empirical relations for ρ for the thin-film dielectric materials of interest (SiO₂, Si₃N₄ and Al₂O₃) can be well approximated by simple exponential dependences on electric field. This is responsible for the success of the present approach, since it leads to a further simplification in the analytical solution for threshold voltage shifts (using the well-known equivalent circuits of dual-dielectric structures) of NVM devices. It is shown that a wide variety of NVM structures can be described in terms of two technology parameters, β₁ and β₂, which contain the geometry, materials, and relevant parameters describing the charging (write/erase) mechanisms. No adjustable parameters are present. Predictions of threshold voltage shifts are found to be in reasonable agreement with experiment. This model is well suited to facilitate computer-aided-design (CAD) of NVM devices. While it is recognized that this model ignores several physical details (e.g. bulk charging of dielectric layers) and is therefore not universal, it nevertheless can be readily used to predict the first-order circuit behaviour of most NVM devices, when β₁ and β₂ are properly obtained.