Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology

A low-power 16:1 multiplexer (MUX) IC using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been successfully designed and fabricated. To minimise power consumption, the collector current density of each HBT was optimised taking into account the required operating speed and the number of fan-outs. Up to 47 Gbit/s error-free operation was confirmed with low power consumption of about 3.2 W. These results demonstrate that InP/InGaAs HBT technology is attractive for fabricating over 40 Gbit/s, low-power medium-scale-integration (MSI) circuits.     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

带复合掺杂层的InP基HBT新结构

对用于光电集成(OEIC)的InP基异质结双极性晶体管(HBT)进行了分析,提出了一种新的集电区外延结构,该结构在集电极区和次集电区之间插入一层特定厚度的P-InGaAs和两层特定厚度但不同掺杂浓度的n-InP层,从仿真结果出发对各种不同结构做出分析,发现这种新结构克服了双异质结双极晶体管的电流阻挡效应,同时很好地解决了传统的双HBT(DHBT)的电子堆积效应和SHBT反向击穿电压低的问题.     

47.8 GHz InP HBT quadrature VCO with 22% tuning range

A 38-47.8 GHz quadrature voltage controlled oscillator (QVCO) in InP HBT technology is presented. The measured output power is -15 dBm. The simulated phase noise ranges from -84 to -86 dBc/Hz at 1 MHz offset. It is believed that this is the first millimetre-wave QVCO implemented in InP HBT technology as well as the highest measured oscillation frequency for any QVCO     

基于InP HBT工艺的超高速静态及动态分频器

<正>磷化铟异质结双极型晶体管(InP HBT)具有超高速、高器件一致性、高击穿等优点,在超高速数模混合电路应用方而具有独特优势。南京电子器件研究所基于76.2mm InP HBT圆片工艺,研制出60 GHz静态分频器以及92 GHz动态分频器。图1为静态分频器测试结果,此电路可在2~60 GHz范围内实现二分频。图2为动态分频器测试结果,此电路可在75~92 GHz范围内实现二分频。     

基于InP HBT工艺的100 GHz静态及动态分频器

<正>南京电子器件研究所基于76.2 mm(3英寸)InP HBT圆片工艺,研制出最高工作频率达100 GHz的静态分频器以及动态分频器。图1为静态分频器测试结果,此电路可在2~100 GHz范围内实现二分频。图2为动态分频器测试结果,此电路可在75~100 GHz范围内实现二分频。     

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.     

基于InP HBT的5 GS/s采样保持电路设计

基于0.7μm、ft=280 GHz的InP HBT工艺设计了一种双开关宽带超高速采样保持电路。芯片面积1.5 mm×1.8 mm,总功耗小于2.1 W。仿真结果表明,电路可以在5 GS/s采样速率下正常工作。当采样速率分别为5 GS/s和1 GS/s时,在输入信号功率为4 d Bm的情况下,采样带宽分别为16 GHz和20 GHz;在输入信号功率为4 d Bm且其频率小于5 GHz的情况下,电路的SFDR分别不低于43 d Bc和50 d Bc。     

An Ultra-Wideband 7-Bit 5-Gsps ADC Implemented in Submicron InP HBT Technology

An ultra-wideband 7-bit 5-Gsps analog-to-digital converter (ADC), fabricated in a 4-level interconnect, 0.8 mum Indium-Phosphide (InP) heterojunction bipolar transistor (HBT) technology, is presented. This monolithic folding/interpolating ADC includes a front-end master-slave sample and hold and a pipeline stage sample and hold. The chip achieves 6 effective number of bits (ENoB) Nyquist performance at a sample rate of 5 Gsps, while dissipating 8.4 W. Furthermore, an ENoB performance of greater than 5.7 is maintained at analog input frequencies up to 7.5 GHz. This effective resolution-bandwidth product performance is significantly higher than any other previously reported monolithic ADC with sample rate ges 3 Gsps.     

Measurement of base and collector transit times in thin-base InGaAs/InP HBT

The influence of base thickness reduction on performances of heterojunction bipolar transistors (HBTs) is examined. HBT structures are grown, with a base thickness in the range 25-65 nm and doping concentration from 3/spl times/10/sup 19/ to 6/spl times/10/sup 19/ at/cm/sup 3/. Base transit time is accurately extracted from total base-collector transit time, and described using a simple drift-diffusion approach. This model, however basic, shows very good agreement with measurements when usual parameter values are used. A 0.13-ps transit time reduction is measured when thinning the base from 65 to 25 nm. The thinnest base structure presents a 0.08 ps transit time, allowing a 250 GHz f/sub t/ operation at 270 kA/cm/sup 2/ emitter current density.     

Low-power 50 Gbit/s InP HBT 1:4 demultiplexer IC with multiphase clock architecture

An InP HBT 1:4 demultiplexer IC with a multiphase clock architecture is described that reduces the number of circuit elements and power consumption while maintaining operating speed. The IC operated at 50 Gbit/s with 1.17 W power consumption at a supply voltage of -4.5 V. Compared to an IC with a conventional tree-type architecture using the same InP HBTs, the power consumption is less than half while the operating speed of 50 Gbit/s is maintained.     

A 75 GHz regenerative dynamic frequency divider with active transformer using InGaAs/InP HBT technology

This letter presents a high speed 2:1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7 μm InP DHBT technology with f_T of 165 GHz and f_max of 230 GHz. The circuit includes a two-stage active transformer, input buffer, divider core and output buffer. The core part of the frequency divider is composed of a double-balanced active mixer (widely known as the Gilbert cell) and a regenerative feedback loop. The active transformer with two stages can contribute to positive gain and greatly improve phase difference. Instead of the passive transformer, the active one occupies a much smaller chip area. The area of the chip is only 469×414 μm² and it entirely consumes a total DC power of only 94.6 mW from a single -4.8 V DC supply. The measured results present that the divider achieves an operating frequency bandwidth from 75 to 80 GHz, and performs a -23 dBm maximum output power at 37.5 GHz with a 0 dBm input signal of 75 GHz.     

基于InP HBT工艺的12位8GSps超高速数模转换器设计

设计了一种基于0.7μm的In P HBT工艺设计的12位8GSps的电流舵型数模转换器(DAC)。采用双采样技术,将输出采样率提高为时钟频率的两倍。并且将双采样开关与电流开关分离以减小码间串扰。借鉴常开电流源法改进了电流源开关结构。新的结构增大了输出阻抗和稳定性,抑制了谐波失真,提高了芯片动态性能。通过仿真结果得到,这款芯片功耗2.45 W,实现了0.4 LSB的微分非线性误差(DNL)和0.35 LSB的积分非线性误差(INL)。低频下无杂散动态范围(SFDR)为71.53 d Bc,信号频率接近奈奎斯特频率时最差的SFDR为50.54 d Bc。在整个第一奈奎斯特域内,SFDR都大于50 d Bc,满足高端测试仪器的应用要求。     

Submicron-gate InP power MISFET's with improved output powerdensity at 18 and 20 GHz

The microwave characteristics at 18 and 20 GHz of submicron-gate indium phosphide (InP) metal-insulator-semiconductor field-effect transistors (MISFETs) for high output power density applications are presented. InP power MISFETs were fabricated with 0.7 μm gate lengths, 0.2 mm gate widths, and drain-source spacings of 2, 3 and 5 μm. The output power density was investigated as a function of drain-source spacing. The best output power density and gain were obtained for drain-source spacings of 3 μm. At 18 GHz output power densities of 1.59 W/mm with a gain of 3.47 dB and a power-added efficiency of 20.0% were obtained for a drain-source spacing of 3 μm. At 20 GHz output power densities of 1.20 W/mm with a gain of 3.17 dB and a power-added efficiency of 13.6% were obtained for a drain-source spacing of 3 μm     

Fully-integrated GaAs HBT power amplifier MMIC with high linear output power for 3 GHz-band broadband wireless applications

A high linear output power two-stage GaAs heterojunction bipolar transistor (HBT) power amplifier MMIC is reported. The input, interstage and output matching circuits are designed for wideband and low-voltage operations, and are fully integrated into an MMIC chip. The power amplifier measured with 54 Mbits 64-QAM OFDM signals at a collector supply voltage of 3.3 V showed linear output power of higher than 23.2 dBm at an error vector magnitude of 3.0% in a frequency range 3.3-3.6 GHz     

QUASI-PLANAR INTEGRATION OF AN InGaAsP/InP DOUBLE COLLECTION REGION HBT AND AN EDGE-EMITTING LED WITH Mn DOPED ACTIVE LAYER

A monolithically integrated lnGaAsP/lnP device including an HBT and an E-LED wasfabricated with quasi-planar structure using Mn doped active laver and selective Zn diffusion as well aspolyimide protection.300 ps rise time of the HBT was achieved together with BV_(ceo) larger than 8V and theoffset voltage smaller than 30 mV.     

Current drifting behaviour in InP MISFET with thermally oxidised InP/InP interface

Inversion-mode InP MISFETs with a thermally oxidised InP/InP interface have been fabricated. The devices exhibit fairly stabilised drain-current/time characteristics compared with those of the conventional devices reported so far. The MIS interface properties are also discussed.     

0.1-42 GHz InP DHBT distributed amplifiers with 35 dB gain and 15 dBm output

An InP double hetero-junction bipolar transistor (DHBT) distributed power amplifier MMIC with 35 dB gain, 42 GHz bandwidth and 15 dBm output power is reported. This represents the highest power and largest gain reported over this bandwidth from a single chip HBT amplifier. A lumped preamplifier with a novel distributed output is used to obtain high gain and wide bandwidth at these power levels.     

10 GHz full-rate clock and data recovery circuit in 0.18 /spl mu/m CMOS without external reference clock

The design of a fully monolithic integrated 10 GHz full-rate clock and data recovery (CDR) circuit in 0.18 /spl mu/m digital CMOS technology, which employs an injection phase-locked loop (PLL) technique is presented. The CDR operating without the external reference exhibits a capture range of 200 MHz while consuming 205 mA current from 1.8 V supply including the output buffer. The recovered clock signal with 250 mV/sub pp/ pseudorandom bit Sequence input data of length 2/sup 31/-1 exhibits 7.9 ps of peak-to-peak (p-p) and 1.1 ps of root-mean-square (RMS) jitter. The measured clock phase noise at 1 MHz offset is approximately -109 dBc/Hz.     

SAR-retrieved wind in polar regions-comparison with in situ data and atmospheric model output

European remote sensing (ERS) satellites synthetic aperture radar (SAR) wind retrievals using CMOD-IFR2 are, for the first time, retrieved in the marginal ice zone (MIZ) and in Arctic coastal areas and compared with in situ observations from reseach vessels (RVs) and output from a high-resolution atmospheric model. The root mean squares (rms) of the comparisons were 1.6 m s/sup -1/ and 2 m s/sup -1/, respectively. The spatial variation of the SAR wind fields established a decrease in wind speed close to the ice edge for the late summer situations where the wind was along the ice edge with the ice to the left. This decrease is believed to be due to changes in atmospheric stability, possibly through development of an internal boundary layer caused by the cold ice cover and melt water. Lower wind speed near the ice edge is confirmed by the atmospheric model and the in situ observations. Furthermore, good results are obtained from SAR wind retrieval in leads when compared with model output during a cold-air outbreak. Routine measurements in the MIZ are useful for estimating the wind stress, and therefore SAR may play an important role in this region. Finally, the identification of a jet out from Hinlopen Strait in the Svalbard region and low wind wakes along the coast in the SAR-retrieved wind field is confirmed by in situ observations as the RV moves through the region. The jet is also confirmed by the atmospheric model, which is able to reproduce the situation.