An I/Q channel 12-bit 120?MS/s CMOS DAC with deglitch circuits

This paper describes an I/Q channel 12bit 120?MS/s DAC with deglitch circuits. The proposed DAC implemented in a 0.35???m CMOS n-well process employs three stage 4 bit thermometer decoders and deglitch circuits to minimize glitch energy and linearity error. The measurement results show a ±1.5?LSB/±1.3?LSB of INL/DNL and 31 pV·s of glitch energy. ENOB and SFDR are measured to be 10.5 bit and 71.09?dB at sampling frequency of 120?MHz and input frequency of 1?MHz with a total power consumption of 105?mW. Linearity error between I-channel DAC and Q-channel DAC is measured to be approximately 1.5?mV, i.e. the accuracy of 13 bit.     

A low glitch 14-b 100-MHz D/A converter

A low glitch 14-b 100-MHz current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSB's) into 15 equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. A bidirectional thin-film trim network and high β n-p-n devices reduce the amount of laser trimming required to achieve 14-b accuracy, resulting in less post-trim degradation of DAC linearity over temperature and the life of the chip. The converter has been fabricated in a 4-GHz/1.4-μm BiCMOS technology and exhibits a measured glitch energy of 0.5 pV·s (singlet). Settling time to within ±0.012% of the final value is ⩽20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at an update rate (f_CLK) of 10 MHz and an output frequency (f_OUT) of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09×4.09 mm including bond pads and electrostatic discharge (ESD) protection devices     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

A low-glitch binary-weighted DAC with delay compensation scheme

This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Ω termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 μm CMOS technology and dissipates 19 mW from a single 1.8 V power supply.     

Digital Modulator with Bandpass Delta-Sigma Modulator

A digital quadrature modulator with a bandpass -modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f_s/4, –f_s/4 (f_s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm² (0.13 m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).     

A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f _in = 1.83, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.     

A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis

A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-$mu$m SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 $Omega$ loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si.      

A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon–germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm² and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation.     

Novel Ion-Lens Configurations: A Further Step to 2-nm Ion-Beam Lithography

Composite axially symmetric immersion ion lenses are considered that consist of an electrostatic and a magnetic lens. For the first time, their performance is evaluated over the entire range of operating conditions: from the case of a zero magnetic field to the case of a zero ion energy on the target. Operating conditions are characterized in terms of = W _t/W ₀, where W ₀ is the energy of an ion at the boundary of the region in which the trajectories are parallel to the axis and W _t is that on the target. For the first time, simple analytical approximations are derived for C _c/r, C _s/r, f/r, and NI, where C _c is the chromatic-aberration coefficient, C _s is the third-order spherical-aberration coefficient, f is the focal distance, NI is the magnetomotive force of the coil, and r is the outer radius of the coil. The behavior of the four quantities is explored as a function of . The following conclusions are drawn: (i) The aberrations are maximum for a zero magnetic field. (ii) The aberration coefficients decrease monotonically with increasing NIand decreasing , the lens changing from an accelerating to a decelerating one. (iii) If , then C _s/r – ^1/4, C _c/r – ^1/6, f/r– ^1/3, and NI – ^–1/2. (iv) The lenses are suitable for resistless heavy-ion projection lithography and can provide 20 × 10¹¹ pixels of area 2 × 2 nm² for an exposed area of 3 × 3 mm². (v) Used in heavy-ion microprobe systems, the lenses could enable resistless lithography over much larger areas than existing equipment.     

A 50-MHz CMOS amplifier channel for a laser radar

An integrated CMOS amplifier channel consisting of a transimpedance preamplifier, postamplifiers, and gain control circuitry has been designed for the receiver of a pulsed time-of-flight laser radar. The measurement results, a total transimpedance ofZ _t 250 k with a bandwidth ofBW 65 MHz and an input-referred noise current ofi _ni 7 pA/Hz, show that a range measurement resolution of centimeter/decimeter class could be achieved by detecting the edge of the received laser pulse.     

Very high-speed and high-accuracy current-steering CMOS D/A converter using a novel 3-D decoder

In this paper a 10-bit 1.2-GSample/s Nyquist current-steering CMOS digital-to-analog converter (DAC) is presented. Segmentation (90%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a novel 3-D thermometer decoding method which reduces the area, power consumption, and the number of control signals of the digital section. Simulation results show that the spurious-free-dynamic-range (SFDR) in Nyquist rate is better than 65 dB for sampling frequency up to 1.2-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates at only 2.4 V. Total power consumption in Nyquist rate measurement is 149 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.97 mm².     

Change in d.c. and 1/f noise characteristics of n-submicron MOSFETs due to hot-carrier degradation

Hot-carrier stress and its influence on d.c. and 1/f noise characteristics in submicron n-channel MOSFETs was investigated. From a 0.5 μm CMOS technology we observed a negative shift in the threshold voltage and a decrease in the drain current. The degradation increases the series resistance on the drain side. In most cases, the relative 1/f noise in the drain current also increases. A degraded device is often found to be noisier in its reverse mode than in its normal mode. The novel material is that the normalized 1/f noise analysis in terms of the 1/f noise parameter α is a more sensitive diagnostic tool for hot-carrier degradation in submicron MOSFETs than S_I (

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) and some results are qualitatively explained in terms of mobility fluctuations.     

A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC

This paper presents a 6-bit very high-speed, low-power digital-to-analog converter (DAC). It is based on a current steering binary weighted architecture and achieves 10-bit static linearity without calibration. Due to the use of a pseudo-segmented structure instead of a thermometer decoder, the operating speed of the converter can be up to 4.5 GS/s. The DAC occupies 0.4 mm $times$ 0.5 mm in a standard 130 nm CMOS technology. A spurious-free dynamic range (SFDR) of more than 36 dB has been measured over the complete Nyquist interval at sampling frequencies up to 3 GS/s. The power consumption at a 3 GHz clock frequency for a near-Nyquist sinusoidal output signal equals 29 mW .      

Identification of Trapping Effects and Ion Neutralization at the Insulator/Semiconductor Interface of MIS Structures from Dynamic Current–Voltage Characteristics of Ion Depolarization

The manifestations of ion traps, ion neutralization, and minority carrier generation at the insulator/semiconductor interface (hereafter, interface for brevity) in MIS structures are judged from isothermal dependences of ion depolarization current J and high-frequency capacitance C _s of the depletion layer in the semiconductor on gate potential V _g and the rate of potential change _v = dV _g/dt = const. In the general case, even for a single type of mobile ions in the insulator, the dynamic current–voltage characteristics (CVCs) may exhibit three current peaks. The transfer of some nonlocalized (free) ions at the interface through the insulator, depletion of ion traps, and decomposition of neutral ion–electron associates are responsible for the peaks. The sequence and number (down to one) of the peaks depend on the activation energies of the associated processes, value of _v, and energy of activation of minority carrier generation. Depending on these parameters, the peaks may appear, disappear, or merge into a broad peak, which may erroneously be identified as a result of the depletion of ion traps that have an energy spectrum. In other words, the CVC with a single peak does not necessarily mean that there exist several types of mobile ions. From the J, C _s = f(T, V _g, n ₀, _v) families, one can discriminate between purely ionic and electronic phenomena and identify free, neutralized, and/or trapped ions present at the interface (here, T is the temperature and n ₀ is the initial total surface concentration of particles (ions) and neutral associates at the interface).     

Design of a 12-bit high-speed CMOS D/A converter using a new 3D digital decoder structure useful for wireless transmitter applications

In this paper a 12-bit Nyquist current-steering digital-to-analog converter (DAC) is implemented using TSMC 0.35 μm standard CMOS process technology. The proposed DAC is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for it leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1 GHz sampling frequency. Simulations indicate that the DAC has an accuracy better than 10.7-bit for upcoming higher data rate standards (IEEE 802.16 and 802.11n), and a spurious-free-dynamic-range (SFDR) higher than 64 dB in whole Nyquist frequency band. The post layout four corner Monte-Carlo simulated INL is better than 0.74 LSB while simulated DNL is better than 0.49 LSB. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. Active area of chip is 1.37 mm².     

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18 μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01 pV s. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33 LSB and a differential nonlinearity (DNL) of 0.14 LSB. The DAC can achieve a maximum measured SFDR of 65.19 dB for 97.50 kHz signal at a sampling rate of 100 MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07 MHz signal the measured SFDR is 56.84 dB at 100 MSPS sampling rate. At 50 MSPS sampling frequency and 146 kHz signal the SFDR of the DAC is 65.90 dB. The measured SFDR at 538 kHz signal is 63.62 dB for a sampling rate of 50 MSPS. Measured third order intermodulation distortion of the DAC is 58.55 dB, for a dual tone test with 1.03 MHz and 1.51 MHz signals at 50 MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06 MHz signal and 100 MSPS sampling frequency, the power dissipation of the DAC is 20.74 mW with 1.8 V supply.     

The shape of self-assembled InAs islands grown by molecular beam epitaxy

We have determined the shape of InAs quantum dots using reflection high energy electron diffraction. Our results indicate that self-assembled InAs islands possess a pyramidal shape with {136} bounding facets. This shape is characterized by C_2v symmetry and a parallelogram base, which is elongated along the direction. Cross-sectional transmission electron microscopy images taken along the [110] and directions as well as atomic force microscopy images strongly support the {136} shape. Furthermore, polarization-resolved photoluminescence spectra show strong in-plane anisotropy, with emission predominantly polarized along the direction, consistent with the proposed quantum dot shape.     

On the structure of the privacy hierarchy

An N argument function f(x ₁,...,x _N ) is called t-private if a protocol for computing f exists so that no coalition of at most t parties can infer any additional information from the execution, other than the value of the function. The motivation of this work is to understand what levels of privacy are attainable. So far, only two levels of privacy are known for N argument functions which are defined over finite domains: functions that are N-private and functions that are (N – 1)/2-private but not N/2-private.In this work we show that the privacy hierarchy for N-argument functions which are defined over finite domains, has exactly (N + 1)/2 levels. We prove this by constructing, for any N/2 t N – 2, an N-argument function which is t-private but not (t + 1)-private.This research was supported by US-Israel Binational Science Foundation Grant 88-00282.     

A Low-Power Class-AB Negative-Feedback Output Amplifier for a 1 V LW Receiver

The design and the measurement results are presented of a low-voltage (1 V) class-AB negative-feedback output amplifier. The amplifier is designed for use in a single-chip LW receiver, which can be put completely in the ear, supplied by a 1 V power supply and is capable of driving a load with an impedance of 30 . The maximum output current of the amplifier is approximately 2.5 mA and its quiescent current is approximately 100 A. This high efficiency is obtained by means of biasing two of the three amplifying stages in class-AB operation. With the aid of negative feedback, the total harmonic distortion for a single 1 kHz tone at 1 mA level is kept below 1%. The output amplifier is integrated in a bipolar process which has vertical NPN transistors with a maximum f _T of 5 GHz and lateral PNP transistors with a maximum f _T of 20 MHz.     

一种氮化镓高迁移率晶体管的栅电流噪声模型

This work presents a theoretical and experimental study on the gate current 1/f noise in Al Ga N/Ga N HEMTs. Based on the carrier number fluctuation in the two-dimensional electron gas channel of Al Ga N/Ga N HEMTs, a gate current 1/f noise model containing a trap-assisted tunneling current and a space charge limited current is built. The simulation results are in good agreement with the experiment. Experiments show that, if Vg Vx, gate current 1/f noise comes from not only the trap-assisted tunneling RTS, but also the space charge limited current RTS. This indicates that the gate current 1/f noise of the Ga N-based HEMTs device is sensitive to the interaction of defects and the piezoelectric relaxation. It provides a useful characterization tool for deeper information about the defects and their evolution in Al Ga N/Ga N HEMTs.