基于单片机的数字频率计设计

设计了一款基于单片机的数字频率计。电路有信号整形、信号分频、单片机控制及显示模块等部分组成。实现对周期信号的频率测量,测量结果在LCD显示器上显示。测试幅度在0.5V～5V;测试频率在1Hz～1MHz;测量误差≤0.1%。     

多功能计数器的设计

该系统由单片机89S52控制模块,程控宽带放大模块,整形模块,FPGA内频率、相位差测量模块等构成,采用等精度测频法测出频率和周期,可测量有效值为0.01～5 V,频率范围1 Hz～20 MHz信号的频率、周期信号,精度高达10-6。采用计数法测量相位差,该系统可测量有效值0.5～5 V,频率10 Hz～100 kHz信号的相位差,精度为1°。系统功能由按键控制,测量结果实时显示,人机界面友好。     

多功能计数器的设计

该系统由单片机89S52控制模块,程控宽带放大模块,整形模块,FPGA内频率、相位差测量模块等构成,采用等精度测频法测出频率和周期.可测量有效值为0.01～5 V,频率范围1 Hz～20 MHz信号的频率、周期信号,精度高达10-6.采用计数法测量相位差,该系统可测量有效值0.5～5 V,频率10 Hz～100 kHz信号的相位差,精度为1°.系统功能由按键控制,测量结果奕时显示,人机界面友好.     

基于改进型ADPLL的频合器设计与实现

本文采用VHDL语言完成了基于改进型全数字锁相环(ADPLL)的频率合成器设计与实现。本设计使用自适应数字分频器克服了锁相环同步带的限制。频率合成器的输入信号频率从1Hz到10MHz范围,输出信号相位以输入信号为基准,输出信号频率从1Hz到10MHz由用户设定,频率分辨率为1Hz。输出信号与输入信号的最大相差可控,输出信号频率的最大频差可控。     

基于PSoC芯片的两路高精度频率测量系统设计

针对在脉冲频率测量中,测量精度低、频率范围窄等问题,提出了一种基于PSoC芯片的两路信号频率测量系统。采用PSoC芯片CY8C29666作为系统核心,以改进的多周期同步测频法为理论基础,结合PSoC芯片集成度高、系统资源丰富、配置灵活、稳定抗干扰的优点,实现了对0.1 Hz～10 MHz之间两路信号频率的高精度测量,并结合实验结果进行了精度分析。     

基于DDS技术的高频信号源设计与实现

介绍了一种基于直接数字频率合成(DDS)技术的高频信号源的设计与实现.该系统以单片机STC89C54RD+和DDS芯片AD98S1为核心,产生正弦波信号,通过AD835与THS6002实现幅度数控调整,最终实现了输出频率、幅度和占空比可调的正弦波和脉冲波信号.实测结果表明:该高频信号源输出频率为0～70 MHz;幅度为0～10V(P-P);脉冲信号的占空比为5％ ～95％,且都实现了数控可调,具有信号的频率误差小、分辨率高和幅度稳定等优点.     

AS3341通用电子计数器

AS3341型通用电子计数器是采用 Z80微处理机的新型测量仪器,在 CPU 控制下进行测量和数据的采集、处理。这样,使得该仪器具有一些传统的计数器所难以达到的特点。仪器具有两个相同的高阻通道 A 和 B,其工作频带为0～100MHz,灵敏度为有效值50mv(0～50MHz)或100mV(50MHz～100MHz)。每个通道均可选择交流或直流耦合;正沿或负沿触发;衰减10倍(×10)或直通(×1);自动触发电平或预置触发电平等工作状态。A、B 两通道除分离外,还可以公共耦合方便测量。仪器采用输入同步、多周期平均等技术,时标为10ns,实现了高频、低频的等分辨率测量,大大地提高低频的测量精度。仪器除可测量频率、周期、时间间隔外,还可以进行时间间隔延迟、比率、累计数、单次脉冲串频率的测量,并可扩展 A、B 两通道相位差和 B 通     

常见的频率比较仪器—频率计

衡量一个频率计的优劣首先要看其功能。常用的频率计都会有频率与周期测量功能．能满足一般的测试需要。高档的频率计一般称自己为多用计数器（Universal Counter）,大多具备两个相同的通道,可以测量信号的脉冲上升／下降时间和占空比．可以计数,甚至具备统计分析功能。增加了第二通道后．就可以比较两个信号,比如测量时间间隔、相位比较、直接频率比较。     

基于单片机和FPGA的多功能计数器的设计

以89S52单片机和EP1C6Q240C8型FPGA为控制核心的多功能计数器.是由峰值检波、A/D转换、程控放大、比较整形、移相网络部分组成.可实现测量正弦信号的频率、周期和相位差的功能.多功能计数器采用等精度的测量方法,可实现频率为1 Hz～10 MHz、幅度为0.01～5 Vrms的正弦信号的精确测频,以及频率为10 Hz～100 kHz、幅度为0.5～5 Vrms的正弦信号精确测相.液晶显示器能够实时显示当前信号的频率、周期和相位差.该多功能计数器精度高,界面友好,实用性强.     

自动频率测量仪电路设计

采用由上至下逐层的方法,进行了自动频率测量仪电路的设计、综合、优化、仿真与验证。整个电路用一片PLD可编程器件作为载体,它可以测量频率在1Hz～10MHz范围的周期性信号。     

Pulsewidth control loop with a frequency detector for wide frequency range operation

A pulsewidth control loop (PWCL) with a frequency detector for wide frequency range operation is presented. The proposed PWCL is implemented with a duty cycle controlled circuit and frequency detector to correct the wide range frequency and duty cycle of the input clock. The duty cycle controlled circuit is able to modify the gain with different frequency and duty cycle ranges. The frequency and duty cycle of the input clock are detected by the frequency detector. The frequency detector is based on a ring oscillator and the input clock duty cycle and frequency are detected within two input clock cycles. The proposed circuit has been fabricated in a 0.35 μm CMOS technology. The proposed circuit generates the output clock of 50% duty cycle with the input range from 20% to 80% and frequency range 50–800 MHz. The measured duty cycle error is less than 1% within the frequency range from 50 MHz to 800 MHz.     

All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles

An all-digital delay-locked loop (DLL) and an all-digital pulsewidth-control loop (PWCL) with adjustable duty cycles are presented. For the DLL, by using the flash time-to-digital conversion, both the phase alignment and the duty cycle of the output clock are assured in 10 cycles. For the PWCL, the sequential time-to-digital conversion is adopted to reduce the required D-flip-flops and lock within 28 cycles. For both of the proposed circuits, the requirement of the input clock with 50% duty cycle is eliminated. The proposed circuits have been fabricated in a 0.35-/spl mu/m CMOS process. The proposed DLL generates the output clock with the duty cycle of 25%, 50% and 75%, and the operation frequency range is from 140 to 260 MHz. For the proposed PWCL, the duty cycle is adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 to 600 MHz.     

1?MHz–3.5?GHz, wide range input duty 50% output duty cycle corrector

A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5?GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1?MHz. The test chip is fabricated using SMIC 0.18???m CMOS process. The experiment results show that the frequency range of the input signal was 1?MHz?C3.5?GHz, and the duty cycle range of the input signal is from 0.1?C99.9%. The peak-to-peak jitter and power dissipation are 33.3?ps and 0.6?mW, respectively, at an operating frequency of 2?GHz.     

High-quality photonic sampling streams from a semiconductor diodering laser

We report on the development of an ultralow-noise, external-cavity, actively mode-locked semiconductor diode laser for application in next-generation photonic sampling systems. A summary of harmonically mode-locked noise characteristics in a 65-MHz ring cavity is presented through the range of pulse repetition frequencies between 130 MHz and 8.3 GHz (2nd-128th harmonic). Important implications regarding the use of gain-versus-loss modulation as the active modelocking mechanisms are discussed. We also report what are, to our knowledge, the lowest noise characteristics achieved to date for a semiconductor diode laser operating at 10 GHz. Individually optimized results of 0.12% rms amplitude noise (10 Hz-10 MHz), and 43 fs rms residual phase jitter (10 Hz-10 MHz) provide a theoretical resolution of 8.6 bits in a 10-GSPS optical analog-to-digital converter. We have also achieved dispersion-compensated pulsewidths; as short as 1.2 ps, and shown successful operation of a novel phase-locked-loop capable of reducing the rms; residual phase noise by as much as 91% within its response bandwidth. Finally, the first measurements of residual phase noise out to the Nyquist frequency (5 GHz) are presented, providing an upper bound on the rms residual phase jitter of 121 fs (10 Hz-5 GHz)     

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100 MHz to 1 GHz. The proposed circuit has been fabricated in a 0.18 μm CMOS technology.     

一种改进的模拟占空比矫正电路

基于PWLL结构的占空比矫正电路虽然克服了传统占空比矫正电路输出时钟上升沿在占空比矫正过程中发生变化的缺点,但其核心电路——频率电压变换电路不能工作在100MHz以上的频率范围,并且随着工作频率的升高,调整范围会变小。采用pullpush电荷泵代替频率电压变换电路,设计了一个工作在200MHz的占空比矫正电路,HSPICE仿真结果表明其调整范围为30%~70%,占空比变化在1个ps以下,达到了设计要求。     

Breakdown Voltages of Step Junctions in Silicon†

A synchronized frequency multiplication scheme based around frequency-dependent delays is outlined. Since these delays are produced by suitable control of standard TTL circuits, the circuit is easy to implement and its output frequency may be extended to over 1 MHz. A useful by-product of this multiplication scheme is a wide-band constant duty cycle generator.     

800MHz800W固态脉冲功放组件

介绍一种大功率固态脉冲功放组件。该组件在 80 0 MHz中心频率处 ,峰值输出功率大于80 0 W,带宽 50 MHz,脉冲宽度 0 .8μs,脉冲工作比 1%。组件性能稳定 ,已用于气象雷达。     

面向电荷泵的占空比可调四相时钟发生电路北大核心

针对传统四相时钟发生电路产生的时钟波形信号易发生交叠、驱动电荷泵易发生漏电等问题，提出了一种占空比可调四相时钟发生电路。电路在每两相可能出现交叠的时钟信号之间都增加了延时单元模块，通过控制延时时间对输出时钟信号的占空比进行调节，避免了时钟相位的交叠。对延时单元进行了改进，在外接偏置电压条件下，实现了延时可控。基于55 nm CMOS工艺的仿真结果表明，在10～50 MHz时钟输入频率范围内，该四相时钟发生电路可以稳定输出四相不交叠时钟信号，并能在1.2 V电压下驱动十级电荷泵高效泵入11.2 V。流片测试结果表明，该四相时钟发生电路能够产生不相交叠的四相时钟波形，时钟输出相位满足电荷泵驱动需求。     

A frequency multiplier for reference frequency in frequency synthesizer systems

A low jitter frequency multiplier, which requires less power, area, and design complexity than reference multiplying PLL or DLL circuits can be used to generate the reference frequency for a low phase noise frequency synthesizer. This paper proposes a mixed signal solution based on the fact that the average DC value of a signal is proportional to its duty cycle. The solution uses a feedback loop with coarse and fine delay resolution to generate a \(90^{\circ }\) phase shifted clock that is used to produce a doubled frequency signal with 50% duty cycle. This method can be used to multiply the input frequency of 40 MHz by multiples of 2, up to 16. The design is implemented in 65 nm UMC CMOS process. Operating from 1.2-V supply, it dissipates 0.46 to 1.2 mA at output frequencies 80–640 MHz, achieving ? 162.3 and ? 139 dBc/Hz phase noise at 1 MHz offset, respectively.