A multiple-terminal gate charging model

A gate charging model considering charging effect at all terminals of a MOSFET is reported in this letter. The model indicates two distinct charging mechanisms existing in P MOSFETs with a protecting device at their gates during plasma processing. The "normal-mode" charging mechanism exists when antenna size at the gate is higher than that at other terminals combined. In contrast, the "reverse-mode" charging mechanism exists in the case of antenna size at the gate lower than that at other terminals combined. The normal-mode mechanism will dominate the charging event when there is no protecting device at the transistor gate or the protecting device provides very low leakage current. On the other hand, the reverse-mode mechanism becomes dominant if the protecting device provides very high leakage current. The normal-mode charging mechanism is limited by the N-well junction leakage while in the reverse-mode mechanism, it is limited by the leakage of the protecting device. The model also suggests that larger N-well junction gives rise to higher charging damage in the normal-mode mechanism while it is opposite in the reverse-mode mechanism. These were confirmed by experimental data. The model points out that a zero charging damage can be achieved at certain combinations of the gate, source, drain and N-well antenna ratio. The knowledge of these transistor terminal antenna-ratio combinations will maximize the effective usage of the charging protection devices in circuit design. The reverse-mode charging mechanism suggests that the use of a high-leakage device at the transistor gate for charging protection may cause an opposite effect when the transistor terminal antenna ratios run into a condition that triggers this mechanism. This implies that PMOS transistors with gate intentionally pinned at ground or low potential in circuits may be prone to charging damage depending on the connectivity of their source, drain, and NW.     

Multiple-terminal gate charging effect - competing/compensating charging behavior

The charging effect from the antenna at the multiple nodes of MOSFET devices was investigated using bulk-CMOS technology. We demonstrated experimentally that the antenna size at source and drain terminals can modulate gate charging behavior, just like that at the gate terminal. However, gate charging damage is lessened when the source and/or drain antenna size increases, which is an effect opposite to that of the gate antenna. The effect can be explained by a multiple-terminal gate charging model, revealing the competing and compensating nature of the incoming charging current among the gate, source, and drain terminal of the MOSFET. The model also indicates a similar effect for the N-well antenna in P MOSFETs. The finding here leads to an application that actually utilizes metal antennae to protect gate oxide in realistic circuits.     

超薄氧化门的等离子体充电损伤机理

探讨了金属氧化物半导体场效应管超薄氧化门在等离子体加工中造成的充电损伤机理,应用碰撞电离模型解释了超薄氧化门对充电损伤比厚氧化门具有更强免疫力的原因.     

Nondestructive DCIV method to evaluate plasma charging damage inultrathin gate oxides

Understanding and minimizing plasma charging damage to ultrathin gate oxides became a growing concern during the fabrication of deep submicron MOS devices. Reliable detecting techniques are essential to understand its impact on device reliability. As the gate oxide thickness of MOSTs rapidly scales down, the conventional nondestructive methods such as capacitor C-V and threshold voltage and subthreshold swing of MOSTs are no longer effective for evaluating this damage in gate oxide. In this paper, the newly developed direct-current current-voltage (DCIV) technique is reported as an effective monitor for plasma charging damage in ultrathin oxide. The DCIV measurements for p-MOSTs with both 50- and 37-Å gate oxides clearly show the plasma charging damage region on the wafers and are consistent with the results of charge-to-breakdown measurements. In comparing with charge-to-breakdown measurement and other conventional methods, the DCIV technique hits the advantages of nondestructiveness, high sensitivity and rapid evaluation     

Effects of wafer temperature on plasma charging induced damage toMOS gate oxide

The effect of wafer temperature on damage to thin MOS gate oxide from plasma has been investigated for the first time. As the wafer surface temperature during an O₂ plasma exposure increases from 145°C to 340°C, the damage measured from charge-to-breakdown (Q_bd) increases dramatically. This result agrees with Fowler-Nordheim tunneling current mechanism for plasma charging and the temperature activated damage model. The increase of damage at higher wafer processing temperature indicates that elevated temperature plasma processes, such as plasma enhanced CVD and Cu etching, can be expected to be more susceptible to charging damage than low temperature plasma processes     

Damage-Less Sputter Depositions by Plasma Charge Trap for Metal Gate Technologies

Damage-free sputter deposition process has been developed for metal gate complementary metal-oxide-semiconductor technology. A plasma charge trap (PCT) was introduced in order to eliminate high-energy particle bombardment during sputter deposition processes. Molybdenum (Mo)-gated PMOSFETs were fabricated using a conventional gate-first process. It is shown that the PCT technology yields excellent characteristics in current drivability, as well as in gate oxide integrity (GOI) such as gate leakage current and charge-to-breakdown$(Q_BD)$. The metal gate was also applied to a nonvolatile memory (NVM), which would require most stringent damage control, and good retention characteristics were demonstrated.     

A gate-charging model for ILD related plasma processes in MOSFETs

A model explaining gate-charging damage in MOSFETs observed during inter-layer-dielectric (ILD)-related plasma processes is reported. It indicates that the charging damage associated with the ILD plasma process can be related to the effect of photoconduction and/or capacitive impedance coupling of plasma potential through the multiple ILD layers. The model leads to a conclusion that by placing a larger-area lower-layer metal (such as Metal-1) plate or polysilicon plate at the gate terminal of MOSFETs, this ILD process-related charging damage can be eliminated or significantly reduced due to a substantial reduction in the gate-to-substrate impedance of the transistors.     

The prospect of process-induced charging damage in future thin gate oxides

Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.     

Impact of wafer charging on hot carrier reliability and optimization of latent damage detection methodology in advanced CMOS technologies

We have studied the possibility to use hot carrier stresses to reveal the latent damage due to Wafer Charging during plasma process steps in 0.18 μm and 0.6 μm CMOS technologies. We have investigated various hot carrier conditions in N- and PMOSFETs and compared the results to classical parametric studies and short electron injections under high electric field in Fowler–Nordheim regime, using a sensitivity factor defined as the relative shift towards a reference protected device. The most accurate monitor remains the threshold voltage and the most sensitive configuration is found to be short hot electron injections in PMOSFET’s. The ability of very short hot electron injections to reveal charging damage is even more evidenced in thinner oxides and the better sensitivity of PMOSFET is explained in terms of conditions encountered by the device during the charging process step.     

The electrostatic charging damage on the characteristics andreliability of polysilicon thin-film transistors during plasmahydrogenation

In this letter, the impacts of electrostatic charging damage on the characteristics and gate oxide integrity of polysilicon thin-film transistors (TFT's) during plasma hydrogenation were investigated. Hydrogen atoms can passivate trap states in the polysilicon channel, however, plasma processing induced the effect of electrostatic charging damages the gate oxide and the oxide/channel interface. The passivating effect of hydrogen atoms is hence antagonized by the generated interface states. TFT's with different area of antennas were used to study the damages caused by electrostatic field     

Modeling of oxide breakdown from gate charging during resist ashing

Plasma damage was observed after exposing an antenna capacitor structure to an O₂ plasma in a single wafer resist asher. The observed early breakdown is well modeled by surface charging caused by plasma nonuniformity. Here, the plasma nonuniformity was induced by gas flow and electrode configuration. The present results agree well with our previous results where magnetic field leads to a nonuniform plasma. In this model, nonuniformity leads to a local imbalance of ion and electron currents which charge up the gate surface and degrade the gate oxide. Using SPICE, a circuit model for the test structure and plasma measurements, the Fowler-Nordheim current through the thin oxide regions at different points on the wafer was calculated and found to agree well with the observed damage. The important implication of this work on oxide reliability is that the modeling gives a clear picture to this breakdown mechanism. The charging model can also be applied to any ashing process in any nonuniform plasma. Moreover, this model provides a physical basis for design rules of device structures for the fabrication of reliable gate oxides in submicron MOS technology     

Effect of plasma poly etch on effective channel length and hotcarrier reliability in submicron transistors

The effective channel length (L_eff)) variation resulting from exposure to the plasma during the poly-etch step was investigated. The plasma induced charging effect was also studied using gate polysilicon antenna structures. It was found that, due to the poly etching, the L_eff variation has a larger impact on the fully processed transistor transconductance characteristics than the charging effect in the gate oxide region. It is believed that the damage in the LDD region, which gives rise to the L_eff variation, imposes a serious hot carrier reliability problem     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Plasma charging damage on ultrathin gate oxides

Capacitor C-V and threshold voltage and subthreshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness     

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.     

Prediction of plasma charging induced gate oxide damage by plasmacharging probe

The plasma processing induced wafer charging damage is predicted by the newly developed SPORT (Stanford Plasma On-wafer Real Time) charging probe. Such a probe can directly measure the spatial charging voltage built up on a wafer surface as well as the charging current from the plasma. Both antenna dependence of damage and charge fluence through a gate oxide due to charging can be calculated from the intersection between plasma I-V characteristic measured by the probe and intrinsic MOS I-V characteristic. This result agrees well with the real MOS capacitor damage data from O₂ plasma processing. Thus, given a fluence criteria, this methodology gives a means for predicting the minimum antenna ratio for observable damage     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

Plasma damage in thin gate MOS dielectrics and its effect on device characteristics and reliability

Plasma process-induced damage continues to be a great threat and concern in the modern CMOS technologies. This article concentrates on NMOS vs. PMOS device sensitivity to plasma charging originating from the various processing steps. This dependence is studied with respect to the gate oxide thickness, and large antenna devices are used to evaluate device yield, latent damage, and residual effect of charging on device performance and reliability. Specific studies are performed to explore the resistance to the charging damage in CMOS devices with a 50 Å gate oxide grown with various oxidation processes.     

Verification and reduction of surface charging during high/medium current implantations by implementing plasma damage monitoring

Dielectric charging damage during IC processing is the result of complex interactions between the wafer environment and the wafer itself. Understanding these interactions and recognizing the relative importance of the different mechanisms capable of causing damage, is essential for successful diagnosis and control of charging damage during wafer manufacturing. Avoiding gate oxide damage due to excessive wafer charging has always been an issue with high current implanters. Whether it is caused by shrinking of device dimensions, or its use as a backup for high current applications, charging level awareness becomes the primary limiting factor for running higher beam currents in medium current implanters. Flooding the wafer with low energy electrons from a plasma flood gun (PFG) which is a self-regulated electron shower, has been the widely accepted means of reducing wafer charging. The effectiveness of the PFG in reducing charging as a function of primary ion current, voltage of electron extraction from the PFG, ion beam positioning and other parameters in a beam path to the wafer have been investigated. This investigation was carried out on medium and high current implanters, VIISta 810HP and VIIStaHC respectively, using the plasma damage monitoring (PDM) technique on metrology tool FAaST350.     

Degradation of submicron N-channel MOSFET hot electron reliabilitydue to edge damage from polysilicon gate plasma etching

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO₂-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors