Low power serial-parallel dynamic shift register

Serial-to-parallel shift registers have a wide range of applications. These registers are commonly found in communication systems and interfaces between electronic peripherals. Presented is a unique low power area efficient 128-bit serial-to-parallel shift register design that contains only four transistors per stage. The new register uses the capacitive bootstrapping technique to overcome the threshold voltage drop of MOSFETs. This logic family is named non-ratioed bootstrap logic (NRBL). Target applications are dense smart sensor arrays and image sensors.     

A two-phase drive bipolar linear image sensor using zigzag arrangement of PCD shift register elements

A bipolar linear image sensor composed of a 512-bit photodiode array, two 256-bit switch arrays and two 512-bit plasma-coupled device (PCD) shift registers characterized by zigzag arrangement of conductance transistors has been developed. As compared with a conventional PCD image sensor which needs four-phase or six-phase shift pulses to drive the PCD shift registers, the newly developed sensor requires only two-phase shift pulses and greatly simplifies an external driving circuit. In addition, it can be fabricated by using only four photomasks, providing good cost performance.     

A frame-transfer CCD color imager with vertical antiblooming

A high-density 604 (H)× 576 (V) frame-transfer CCD color image sensor is realized with a pixel dimension of 10.0 (H) × 15.6 (V) µm², an image diagonal of 7.5 mm, and a total chip area of 66 mm². On-chip color filters and the use of a triple read-out register result in separate Cy, G, and Ye output signals. The imager is an n-p-n buried-channel CCD which can handle 125 times overexposure with vertical antiblooming. For the calculation of a suitable dopant distribution in the image, storage, and output sections, a four-step procedure has been developed. This procedure has proved to be successful and is much faster than an approach based exclusively on two-dimensional potential calculations.     

A self-scanned solid-state image sensor

An experimental television camera incorporating a completely integrated self-scanned solid-state image sensor has been built. The integrated sensor includes a photosensitive array having 32 400 picture elements, two 180-stage shift register scan generators and associated video coupling transistors. This large-scale integration of more than 100 000 components was carried out in the laboratory entirely by evaporated thin-film techniques. Each element of the photosensitive array comprises one or two photoconductors of CdS or CdS-CASe mixture, each in series with a diode. The 180-stage scan generators utilize 540 CdSe TWF's deposited upon a glass snbstrate. Center-to-center spacing of elements in the array and in the scan generators is 2 mils. The array is scanned at conventional television scan rates permitting the picture to be displayed upon a commercial television receiver. The camera is connected to the receiver either through a cable or through a UHF link with camera and transmitter powered by a self-contained battery. Camera circuits other than the integrated sensor employ conventional transistors and integrated components. Progress toward the development of an improved sensor having more picture elements is outlined.     

RSFQ 1024-bit shift register for acquisition memory

Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of ±23% and ±14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO_x /Nb process with a junction critical current density of 1.0 kA/cm ²     

A 1/2-in, 1.3 M-pixel progressive-scan CCD image sensor employing0.25-μm gap single-layer poly-Si electrodes

A 1/2-in, 1.3 M-pixel progressive-scan interline-transfer charge coupled-device (IT-CCD) image sensor has been developed for low-power and high-sensitivity digital cameras. The image sensor uses 0.25-μm gap single-layer poly-Si for CCD transfer electrodes in order to reduce the power consumption and number of fabrication process steps. The image sensor achieved a low driving voltage (2.1 V) on a horizontal CCD (H-CCD) at a frequency of 24.5 MHz. An original pixel layout and a self-aligned photodiode structure make it possible to achieve a progressive scan pixel with well-controlled photodiode readout characteristics. An output three-stage source follower amplifier with new multioxide transistors, whose gate insulator thickness is thinner than that of a CCD register, is able to attain 17% higher gain than that of the conventional amplifier. The sensor provides low-power (100 mW) and high output sensitivity. The total number of steps for fabricating the sensor was reduced to 70% of that for conventional three-layer poly-Si electrodes     

A new organization area image sensor with CCD readout through charge priming transfer

A new organization for an area image sensor with a wide dynamic range is proposed, in which an XY photodiode-MOS switch array is combined with an analog CCD readout shift register through a "charge priming transfer (CPT)" function. It is shown that use of the CPT makes the transfer of small signal charge from large capacitance vertical transport lines to the horizontal CCD strikingly efficient. The operating principle of the new device organization and some preliminary experimental results with a 404(H) × 256(V) element image sensor are reported.     

Design and characterization of novel read-out systems for a capacitive DNA sensor

This paper presents novel read-out electronic systems for a fast DNA label-less detection. The capacitive shift due to the hybridization effect is monitored by means of a charge sensitive amplifier and a differential stage. The systems provide an A/D conversion and an evaluation of the capacitive shift amount with a resolution of 11 bit. The read-out solutions demonstrate the ability to identify a 0.01% variation on the capacitive value of the sensor. The investigated techniques are suitable for monolithic systems or for a micro-fabricated array of sensors.     

Analog capacitance ROM with IGFET bucket-brigade shift register

A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.     

A 2 million pixel FIT-CCD image sensor for HDTV camera systems

A 1-in optical format frame-interline-transfer charge-coupled-device (FIT-CCD) image sensor with 2 million pixels and an aspect ratio of 16(H):9(V) has been developed for HDTV cameras. The effective number of pixels is 1920(H)×1036(V). In order to decrease the smear level, achieve uniform charge handling capability for the vertical CCD, and eliminate defects that appear as vertical stripes in the image of the device, aluminum wire was put onto the vertical transfer gate to decrease the resistance in the transfer gate and a dual-channel two-phase CCD was utilized for the horizontal shift register operated by a 37.125-MHz clock. As a result, this image sensor has a dynamic range of 72 dB and a sensitivity of 75 nA/lx for light with a color temperature of 2856 K. Smear is reduced to -100 dB by using the FIT-CCD image sensor structure. The horizontal limit is 1000 TV lines. In addition, image lag is negligibly small and below the sensitivity of the measurement instrument     

A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors

A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTTs latching function and the MOSFETs switching function, the number of devices required for the D-FF circuit was greatly reduced to three from the thirty required for the FET-only circuit.     

A 10 K-gate 950 MHz CML demonstrator circuit made with a 1-μmtrench-isolated bipolar silicon technology

A quad 512-b static shift register consuming 1.8 mW/stage designed to demonstrate the capabilities of an advanced bipolar silicon technology is discussed. The process uses 1-μm lithography, trench isolation, polyemitter transistors, polysilicon resistors, and polycide layer for local interconnections. This VLSI circuit (over 35 K transistors, 86-mm² chip) has been implemented on a sea-of-cells structure. An appropriate scheme has been used for the clock distribution. The experimental results show operation at a clock frequency up to 950 MHz     

A 1/3-in 510(H)×492(V) CCD image sensor with mirror imagefunction

A 1/3-in optical format 510(H)×492(V) interline charge-coupled-device (CCD) image sensor with a mirror-image function has been developed. To realize both a normal image and a mirror image, the horizontal shift register (H-CCD) is transferred forward and backward by a four-electrode, quasi-two-phase clock drive. The unit cell size is 9.6(H)×7.5(V) μm². An on-chip microlens has been developed to achieve a sensitivity of 28 mV/lx, which is higher than that of the conventional 1/2-in device. The hole accumulation diode (HAD) sensor used has the advantage of low dark current, negligibly small lag, high blooming suppression, and a variable-speed electronic shutter. The smear reduction level is -83 dB. Horizontal resolution of 330 TV lines is obtained     

An integrated driving circuit implemented with p-type LTPS TFTs for AMOLED

Based on the technology of low temperature poly silicon thin film transistors (poly-Si-TFTs), a novel p-type TFT AMOLED panel with self-scanned driving circuit is introduced in this paper. A shift register formed with novel p-type TFTs is pro- posed to realize the gate driver. A flip-latch cooperated with the shift register is designed to conduct the data writing. In order to verify the validity of the proposed design, the circuits are simulated with SILVACO TCAD tools, using the MODEL in which the paramete...     

Thin-film circuits for scanning image-sensor arrays

Integrated circuits for scanning a photosensitive array at standard television scan rates have been fabricated by evaporated thin-film techniques. These include: 1) A 264-stage parallel-output complementary shift register with a driver stage at each output. 2) A 256-output transistor decoder with video coupling circuits for scanning an array with line storage. A single line of 256 photoconductordiode elements has been included on the same substrate with the decoder. The complementary shift register has been demonstrated to operate at clock frequencies up to 100 kHz. The integrated decoder and line sensor, when driven by two external 16-stage shift registers, has been operated successfully with line storage at frequencies up to 4.8 MHz.     

A new accelerated transfer method for the CPD image sensor

A new charge transfer method for the CPD image sensor is proposed. In this method a high transfer speed is achieved with the use of an accelerated charge priming transfer (CPT) coupler, which consists of the array of the conventional CPT's and inverter amplifiers. This constitution strikingly increases the speed as well as the efficiency of the charge transfer from the vertical transport lines with large capacitance to the horizontal buried-channel charge-coupled (BCCD) shift register. Under a high transfer efficiency of more than 98 percent, a short transfer time less than 1 µs has been attained, independently of the signal charge magnitude.     

An analysis of fixed pattern noise for MOS-CCD type image sensors under quasi-stationary conditions

A theoretical explanation for fixed pattern noise (FPN) is given for the MOS-CCD image sensor with the use of external bias charge. The FPN is ascribed to the fluctuation of the bias charge which is returned from the coupler between the vertical transport line and the horizontal CCD (H-CCD) shift register. It is shown that the FPN is eliminated below -60 dB with respect to the maximum output signal in the case of vertical transfer efficiency of 97% or more.     

A 2/3-in 1187(H)×581(V) S-VHS-compatible frame-transfer CCDfor ESP and movie mode

The authors present a high-resolution frame-transfer charge-coupled-device (CCD) suitable for S-VHS camcorders with an additional full-resolution true electronic still picture (ESP) mode of operation. The CCD sensor is composed of an image section, an intermediate readout register, a storage section, and a second readout register. A resolution of 450 TV lines (H) is obtained in color images by applying cyan-green-yellow complementary stripe color filters on the 1187(H)×581(V) pixels. The operation of the sensor in both conventional video and ESP modes is described. Special attention is paid to the 3-D potential calculations required to obtain a design guaranteeing a high-quality picture. Experimental results are presented     

An improved method for MRI artifact correction due to translational motion in the imaging plane

A computer postprocessing technique is developed to remove MRI artifact arising from unknown translational motion in the imaging plane. Based on previous artifact correction methods, the improved technique uses two successive steps to reduce read out and phase-encoding direction artifacts: First, the spectrum shift method is applied to remove read-out axis translational motion. Then, the phase retrieval method is employed to eliminate the remaining subpixel motion of the read-out axis and the entire motion of the phase-encoding axis. In the presence of noise, to protect edge detection (in the spectrum shift method), two high-density gray-level markers are added, one to each side of the imaging object. Experimental results with an actual MR scan confirmed the ability of the method to correct the artifact of an MR image caused by unknown translational motion in the imaging plane     

An Optical Readout Method Based Uncooled Infrared Imaging System

This paper presents an optical readout method based uncooled infrared imaging system that contains an optical read-out section and a bi-material micro-cantilever arrays (BMCA) detector. The optical read-out section is based on incoherent light spatial filter technique. The read-out section converts the deflection angles of BMCA caused by absorption of infrared (IR) radiation to a visible image through optical filtering operation of the BMCA with a knife-edge filter. A spatial mathematical model is presented to describe the read-out method and its validity is proved. The IR image of a person’s hand obtained through the using of the 100?×?100 BMCA and the 12-bit A/D quantizer demonstrates the ability of the system to create image. The performance test shows that the average Noise-equivalent temperature difference (NETD) of the imaging system can arrive at about 183mK with some areas having a NETD as low as 78mK.