基于GaN 的3. 4~ 3. 6 GHz 高增益Doherty 功率放大器

基于两级功率放大器架构,设计了一款平均输出功率为37 dBm(5 W)的高增益Doherty 功率放大器。 该器件通过增加前级驱动功率放大器提高Doherty 功率放大器的增益,采用反向Doherty 功率放大器架构,将λ/4 波 长传输线放置在辅助功放后端,相位补偿线放置在主功放前端,并使主功放输出匹配网络采用双阻抗匹配技术实现 阻抗变换,如此可扩宽功率放大器的工作带宽。连续波测试结果显示:3. 4~3. 6 GHz 工作频段内,饱和输出功率在 44. 5 dBm 以上,功率饱和工作点PAE 在43. 9%以上;在平均输出功率(37 dBm,5 W)工作点,回退量大于7. 5 dB,功 率附加效率PAE 为36. 8%以上,功率增益在31 dB 以上。     

一种高效率逆F类Doherty射频功率放大器

为了进一步提高射频功放的输出能力,基于GaN HEMT功率器件,采用平衡式结构设计了一款工作频率为3.3 GHz 3.6 GHz的高效率逆F类Doherty结构射频功放。参照功放管的寄生参数等效电路网络,为获得逆F类功放理想的开关特性,设计了具有寄生参数补偿作用的谐波控制网络来抑制功放输出端的二次、三次谐波,同时结合Doherty功放结构特点,使其在6 dB功率回退的情况下仍具有较高的输出效率。仿真后,可得到其在3.3 GHz^3.6 GHz工作频带内的输出功率在40.4 dBm^41.8 dBm内,PAE为66%~77%,最大DE达到82.6%,功率回退6 dB处,功放的DE仍在69%左右,增益平坦度约为±1.5 dB。     

Ultrahigh-efficiency power amplifier for space radar applications

This paper describes a broad-band switch mode power amplifier based on the indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. The amplifier combines the alternative Class-E mode of operation with a harmonic termination technique that minimizes the insertion loss of matching circuitry to obtain ultrahigh-efficiency operation at X-band. For broad-band Class-E performance, the amplifiers output network employs a transmission line topology to achieve broad-band harmonic terminations while providing the optimal fundamental impedance to shape the output current and voltage waveforms of the device for maximum efficiency performance. As a result, 65% power-added efficiency (PAE) was achieved at 10 GHz. Over the frequency band of 9-11 GHz, the power amplifier achieved 49%-65% PAE, 18-22 dBm of output power, and 8-11 dB gain at 4 V supply. The reported power amplifier achieved what is believed to be the best PAE performance at 10 GHz and the widest bandwidth for a switch-mode design at X-band.     

A highly linear and efficient differential CMOS power amplifier with harmonic control

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.     

26 GHz高回退效率Doherty功率放大器

针对功率回退时主路功率放大器不能有效进入饱和状态导致Doherty功率放大器回退效率低的问题,通过降低主路功率放大器的供电电压,实现了高回退效率,同时增大辅路功放管的尺寸弥补了电路的总输出功率。基于0. 1μm GaAs pHMET工艺,设计了一个26 GHz两级非对称的Doherty功率放大器。仿真结果表明,在26 GHz时增益达到16 dB,功放的饱和输出功率为27. 4 dBm,峰值功率附加效率(PAE)为40. 7%,输出功率回退7 dB时PAE仍达到38%,与传统Doherty功率放大器相比具有更高的回退效率,版图的尺寸为3. 2 mm×2. 2 mm。     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

A Wideband Envelope Tracking Doherty Amplifier for WiMAX Systems

We have demonstrated a wideband envelope tracking Doherty amplifier. The amplifier is implemented using Eudyna 10-W GaN high electron mobility transistor. For world interoperability for microwave access (WiMAX) signals of the 802.16d and 802.16e, the Doherty amplifier covers the 90 MHz bandwidth (2.3-2.39 GHz) of the Korea's mobile WiMAX (WiBro). The performance of gain, power-added efficiency (PAE), and relative constellation error (RCE) are nearly uniform for the bandwidth. In order to improve the linearity, we have applied the envelope tracking technique to the gate of the Doherty amplifier. The envelope tracking amplifier delivers a significantly improved RCE performance of 35.3dB, which is an enhancement of about 4.3dB, maintaining the high PAE of about 30% for the 802.16 d signal at an average output power of 35 dBm.     

A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier

This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm². Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P₁ dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P₁ dB is above 10% and the PAE degradation is less than 29%.     

基于GaAs HBT工艺的高增益宽带Doherty功率放大器设计

在传统Doherty功率放大器的基础上,采用砷化镓(GaAs)异质结双极晶体管(HBT)工艺,设计了一款可应用于5G通信N79频段(4.4~5 GHz)的高回退效率MMIC Doherty功率放大器(DPA)。通过在Doherty电路中采用共射-共基结构,并在共射-共基结构中加入共基极接地电容,大幅提升了DPA的增益和输出功率。使用集总元件参与匹配,减小了芯片的面积。仿真结果表明,在目标频段内,增益大于28 dB,饱和输出功率约为38 dBm,饱和附加效率(PAE)为63%,7 dB回退处的效率达到43%。     

Optimized Envelope Tracking Operation of Doherty Power Amplifier for High Efficiency Over an Extended Dynamic Range

This paper presents an optimized envelope tracking (ET) operation of a Doherty amplifier. Compared to the general ET/envelope elimination and restoration transmitter, it has an advantage of the extended dynamic range of 6 dB for the load modulation of a Doherty amplifier. Moreover, by modulating the supply voltage of the carrier amplifier, while that of the peaking amplifier is fixed, the supply modulator provides just half of the current for the same power amplifier output power. It results in a reduced chip size and the crest factor of the supply modulating signal is reduced by 6 dB, enhancing the efficiency of the supply modulator. The designed ET transmitter consisting of the Doherty amplifier and the supply modulator are fabricated in 2- $mu{hbox{m}}$ HBT and 0.13-$mu{hbox{m}}$ CMOS processes, respectively. It presents the efficiency improvement over the broad output power region. Especially at the 16-dB backed-off power level, more than 23% of power-added efficiency (PAE) is achieved. For WiBro application, it shows the PAE of 38.6% at an output power of 24.22 dBm with a gain of 24.62 dB. The error vector magnitude is 3.64%.      

基于双向牵引与谐波抑制的Doherty功率放大器设计

为了提高功率放大器(Power Amplifier,PA)的效率,提出一种基于双向牵引与谐波抑制的对称式Doherty功率放大器(Symmetrical Doherty Power Amplifier,SDPA)结构。该结构在经典DPA 的基础上,首先利用多谐波双向牵引技术获得功放的实际最佳阻抗,然后对主辅功放的二、三次谐波进行抑制,降低了漏极电压电流的重合,最后通过添加补偿线调节主辅功放的功率分配,使得功放整体获得最大的效率。为了验证上述谐波抑制理论与双向牵引技术的正确性,采用GaN 器件设计了一款应用在4G 基站的SDPA。测试结果显示:SDPA 在2.6 GHz 处的小信号增益为12.6 dB,2.5-2.7 GHz 频段内的增益平坦度为±0.75 dB,频带内的S11小于-11.9 dB,在三载波测试时经过数字预失真(Digital Pre-Distortion,DPD)系统纠正后的相邻信道泄漏比(Adjacent Channel Leakage Rate,ACLR)约为-45 dBc,SDPA 在峰值功率点附近的功率附加效率(Power Added Efficiency,PAE)接近60%,在回退点处的PAE约为48%。实验结果验证了该设计方案的可行性。     

一种新型提高射频功率放大器PAE的电路技术

提出了一种新型提高射频功率放大器功率附加效率(PAE)的电路技术,该方法通过滤除二次谐波分量、反射叠加三次谐波分量以提高电路PAE,分析了相位匹配的机制及其影响因素.基于该技术设计了一款功率放大器,仿真结果表明:工作频率为918 MHz时,该功放的P1dB达到了30.05 dBm,功率附加效率达到了58.75%,较普通...     

基于双匹配的高效大功率Doherty功率放大器

针对Doherty功率放大器传统设计方法的不足,提出了一种双匹配设计技术,并给出了实现方法。基于LDMOS器件,用该方法设计了一款饱和功率为55 dBm的Doherty放大器。仿真结果显示,与未采用双匹配法相比,该Doherty放大器的效率改善更好。功率附加效率在6 dB回退点比平衡式放大器改善15%,在回退约8 dB的区间上,整体效率都在40%以上。实测结果表明,该放大器增益约12 dB,在输出回退6 dB的区间上,功率附加效率改善10%。     

基于GaN HEMT的高线性星载Doherty功率放大器设计北大核心CSCD

在射频通信链路中,功率放大器决定了发射通道的线性、效率等关键指标。卫星通信由于是电池供电,对功率放大器的工作效率要求比较高。文章基于GaN HEMT晶体管采用对称设计完成了一款高效率的Doherty功率放大器。测试结果表明:该Doherty功放的功率增益大于29 dB;1 dB压缩点功率(P_(1 dB))大于35 dBm;在35 dBm输出时,其功率附加效率(PAE)大于47.5%,三阶交调失真(IMD3)大于35 dBc;在功率回退3 dB时,其PAE大于37%,IMD3大于32 dBc。     

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...     

250 W HVHBT Doherty With 57% WCDMA Efficiency Linearized to ${-}$55 dBc for 2c11 6.5 dB PAR

A two-way symmetrical Doherty amplifier exhibiting 250 W saturated power has been developed using high-voltage HBT (HVHBT) GaAs technology biased at 28 V on the collector. Greater than 57% collector efficiency at 50 W (47 dBm) average output power has been demonstrated while achieving -55 dBc linearized ACPR at 5 MHz offset using a two-carrier-side-by-side WCDMA input signal with 6.5 dB PAR measured at 0.01% probability on the CCDF. In addition, a two-stage HVHBT lineup exhibiting 450 W (56.5 dBm) peak power has been demonstrated. The output stage consists of a pair of 250 W two-way symmetrical Doherty amplifiers power combined using a low-loss branchline combiner and driven by a single-ended 100 W class AB high-efficiency amplifier. The lineup demonstrated 44% PAE at 100 W (50 dBm) average output power with 25 dB lineup gain while achieving - 55 dBc linearized ACPR at 5 MHz offset using a two-carrier-side-by-side WCDMA input signal with 6.5 dB PAR measured at 0.01% probability on the CCDF. The lineup exhibits 400 W (56 dBm) PldB at 60% PAE CW, with 45% PAE at 6 dB backoff.     

高效率高线性度功率放大器的设计与实现

基于对传统两路Doherty功放存在的问题分析,文中对其结构进行改进,提出了一种新颖的非对称结构。该非对称结构采用相同的功放管,通过变换漏极与栅极电压分别对主辅功放进行负载牵引和源牵引以达到不同的饱和输出功率,从而实现更高的功率回退。基于该理论,结合互调对消技术和多谐波双向牵引技术设计并实现了应用于工作频段为2.57～2.62GHz的TD-LTE直放站功率放大器。在饱和输出功率回退9dB的平均输出功率处,功率附加效率(PAE)为38%,5MHz和10MHz偏移量的相邻信道功率比(ACPR)分别为-41dBc和-50dBc,实测结果显示Doherty功放的参数性能良好,满足TD-LTE直放站要求的同时验证了设计方案的正确性。     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

1.95GHz Doherty功率放大器设计

基于SMIC 0.18 μm RF CMOS工艺,设计了一款1.95 GHz的Doherty功率放大器.为了保持两路功放相位最大一致性,主功放(PA1)和辅功放(PA2)采用了同一种CMOS功率放大器,仅改变其偏压使其工作在不同模式.CMOS功率放大器为工作于AB类的两级放大电路,集成了输入和级间匹配网络;功分器以及λ...     

1.8 GHz Doherty功率放大器小型化技术研究

基于In GaP/GaAs HBT工艺设计了一款工作在1. 8 GHz的三级Doherty功率放大器,第一、二级为驱动级,第三级为Doherty放大器。通过分析Doherty结构,在原有基础上重新设计Doherty电路,使用LC元件替代微带线,减小功率分配网络与合路匹配网络的面积,进而缩小整体电路的面积。将输入、输出匹配网络及功分、合路部分集成至基板上,整体封装尺寸5 mm×5 mm。测试结果表明,芯片输入、输出回波损耗优于-15 d B,放大器整体增益优于33 d B,3 d B压缩点输出功率35 d Bm,其中第三级Doherty放大器峰值功率附加效率(PAE) 47. 9%,8 d B回退点的功率附加效率32. 7%。