流水线阵列乘法器的功耗分析和优化

针对流水线结构阵列乘法器，分别采用寄存器翻转统计和门级翻转率统计的方法进行了功耗分析，创新地提出了一种通过增加判断逻辑进行数据预分流以实现功耗优化的方法。实验结果证明，这种优化方法能够带来明显的功耗节省。类似方法也可普遍用于逻辑行为对称但实现结构不对称的数据通路单元的低功耗设计实现中。     

采用FPGA的低功耗系统设计

结合采用低功耗元件和低功耗设计技术在目前比以往任何时候都更有价值.随着元件集成更多功能,并越来越小型化,对低功耗的要求持续增长.当把可编程逻辑器件用于低功耗应用时,限制设计的低功耗非常重要.本文将讨论减小动态和静态功耗的各种方法,并且给出一些例子说明如何使功耗最小化.     

一种数字信号处理器的地址生成单元设计

介绍了aDSP处理器中地址生成单元的设计。详细讨论了位倒序寻址模式、模块循环寻址模式和快速判零逻辑的设计实现，并使用门控时钟的方法来解决这些复杂结构引起的功耗增加问题。所有设计按照可综合要求进行RTL编码，经过VCS逻辑仿真和Design Compiler综合验证后成功应用于国家863项目高性能低功耗DSP中。     

几种CMOS VLSI的低功耗BIST技术

在分析全扫描内建自测试(BIST)较高测试功耗的基础上,总结出几种CMOS VLSI的低功耗BIST技术方案,包括减少待测电路(CUT)输入端的翻转次数、简化线性反馈移位寄存器(LFSR)结构、部分扫描低功耗BIST方法等.分析结果表明,这些方法不但在保证测试覆盖率的条件下,降低了测试平均功耗和峰值功耗,而且综合应用这几种方法将会使系统功耗指标达到最佳.     

时钟树低功耗设计

功耗和性能是芯片设计中两项重要的指标,为了满足低功耗的芯片设计要求,IC设计者在芯片设计采用各种低功耗技术。本文提出一种基于寄存器状态的时钟网络的构造方法,它以时钟树中网络节点的节点差异为参数建模,与常规方法相比,此算法可以有效降低门控信号的翻转次数,大幅降低时钟网络的功耗。     

一种RTL级数据通路ODC低功耗优化算法

 本文提出了一种具有高计算效率和低硬件开销的门控时钟低功耗优化算法. 该算法在RTL级搜索数据通路的不可观察性（Observability Don′t Care）. 采用RTL级逻辑信号总线ODC模型和基于路径ODC的有向图遍历模型,减少了ODC计算负荷,提升了计算效率,使ODC适用于超大规模集成电路的低功耗优化. 引入数据通路ODC条件概率作为门控信号产生的重要依据,对ODC条件概率高的通路优先插入门控逻辑,可以极低硬件开销实现高效门控时钟网络. 实验结果显示,本算法与传统ODC算法相比计算负荷平均降低8倍,功耗平均下降12.35%,面积开销平均减少13.44%.     

CMOS数字电路低功耗的层次化设计

随着芯片上可以集成越来越多的管子,电路规模在不断扩大,工作频率在不断提高,这直接导致芯片功耗的迅速增长,无论是从电路可靠性来看,还是从能量受限角度来讲,低功耗都已成为CMOS数字电路设计的重要内容。由于不同设计抽象层次对电路功耗的影响不同,对各有侧重的低功耗设计方法和技术进行了讨论,涉及到工艺,版图,电路,逻辑,结构,算法和系统等不同层次。在实际设计中,根据具体应用环境,综合不同层次全面考虑功耗问题,可以明显降低电路功耗。     

基于XNOR/OR逻辑的低功耗最佳极性搜索

 本文通过对XNOR/OR逻辑表达式、信号概率传递算法和极性转换算法的研究,提出了一种基于XNOR/OR逻辑的低功耗最佳极性搜索算法.由于算法所用的成本函数包含功耗和面积两方面因素,因此能实现功耗和面积的同时优化.通过对10个MCNC Benchmark电路的测试表明,算法对最佳极性的搜索相当有效:与极性0时的XNOR/OR电路相比,算法搜索到的最佳极性所对应的电路,功耗和面积平均节省分别达到68.4％和34.2％.     

基于液晶显示屏的低功耗驱动技术

为进一步降低液晶显示器的逻辑功耗,本文以11.6HD、14HD、14FHD为背景,分别从像素结构、驱动技术、驱动电路设计以及背光驱动技术等方面进行了深入研究。首先,研究了不同像素结构(dual Gate+normal像素结构和dual Gate+Z inversion像素结构)下多种像素驱动方法对功耗的影响。接着,研究了像素负载以及像素驱动信号(包括栅极驱动信号和源极驱动信号)对功耗的影响。最后,对比了不同的背光调光方法对功耗的影响。实验结果表明:像素结构、负载大小、驱动方法均对功耗有较大的影响。以14HD为例,点翻转比列翻转会有38.5%的功耗上升;Data load每上升10%,功耗约有8%的上升;VGH每提高1V,功耗上升1.35mW;采用mix-mode调光方式比传统的PWM调光在不同亮度百分比下功耗约降低2%~15%。因此通过对这些功能模块进行优化设计可以有效地降低液晶显示器逻辑功耗。     

基于概率表达式的MPRM电路功耗计算方法

采用基于信号概率的功耗计算模型进行MPRM（Mixed Polarity Reed-Muller）电路功耗优化,信号概率计算是功耗计算的关键.提出一种基于概率表达式的MPRM电路功耗计算方法.该方法兼顾信号概率计算的时间效率和准确性,对MPRM电路中不存在空间相关性的信号通过在电路中传播信号概率的方式计算其信号概率,存在空间相关性的信号则利用概率表达式计算其信号概率,并在电路中传播概率表达式以解决空间相关性问题,在此基础之上根据基于信号概率建立的解析动态功耗和静态功耗计算模型计算电路功耗.为进一步提高时间效率,该方法采用二元矩图表示概率表达式.使用基准电路对所提出方法进行了验证,并与其他采用不同信号概率计算方法的MPRM电路功耗计算方法进行了比较.结果表明所提出方法准确有效.     

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.     

Josephson-logic devices and circuits

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

Efficient statistical approach to estimate power consideringuncertain properties of primary inputs

Power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. In this paper, we present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to uncertainties in specification of primary inputs. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using Monte Carlo-based approaches. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately     

多端I/O系统用BiCMOS连线逻辑电路

为了满足数字通信和信息处理系统多端输入/输出(I/O)、高速、低耗的性能要求,笔者设计了几例BiCMOS连线逻辑电路,并提出了采用0.5 mm BiCMOS工艺,制备所设计的连线逻辑电路的技术要点和元器件参数。所做实验表明了设计的连线逻辑电路既具有双极型逻辑门电路快速、大电流驱动能力的特点,又具备CMOS逻辑门低压、低功耗的长处,而且其扇入数可达3~16,扇出数可达1~18,因而它们特别适用于多端I/O高速数字通信和信息处理系统中。     

A New Static Differential CMOS Logic with Superior Low Power Performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.Muhammad E.S. Elrabaa received his B.Sc. degree in computer Engineering from Kuwait University, Kuwait in 1989, and his M.A.Sc. and PhD degrees in Electrical Engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1995, respectively. His graduate research dealt with Digital BiCMOS ICs and Low-Power circuit techniques. From 1995 till 1998, he worked as a senior circuit designer with Intel Corp., in Portland, Oregon, USA. He designed and developed low power digital circuits for Microprocessors. From 1998 till 2001 he was with the EE department, UAE University as an assistant professor. In 2001, he joined the computer Engineering department, KFUPM University. His current research interests include reconfigurable computing, low-power circuits, and communication circuits. He authored and co-authored several papers, a book and holds two US patents.     

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies.