L波段数字锁相环频率合成器的研究

本文介绍了一种Ｌ波段锁相环频率合成器，频率范围１．１－１．６ＧＨＺ，频率步进为１ＭＨＺ，相位噪声为ε（１０ｋＨｚ）〈－９０ｄＢｃ／Ｈｚ杂散抑制优于５５ｄＢ，输出功率≥０ｄＢｍ。     

2.30GHz—2.70GHz锁相环式频率综合技术研究

本文阐述了一个基本的Ｓ波段锁相式频率综合器，频率范围是２．３０ＧＨｚ－２．７０ＧＨｚ，频率步进为５ＭＨｚ，相位噪声指标为￡（１０ｋＨｚ）〈－９５ｄＢｃ／Ｈｚ，杂散抑制优于５０ｄ，输出功率大于１０ｄＢｍ。     

C波段双频切换低相噪介质稳频振荡器的设计

文章介绍了一种双频切换，低相噪介质稳频振荡器（ＤＲＯ）的设计方法。运用微波ＣＡＤ设计的Ｃ波段ＤＲＯ，其相位噪声可达到－７２～－７５ｄＢｃ／１Ｈｚ／１ｋＨｚ，最佳为－８０ｄＢｃ／１Ｈｚ／１ｋＨｚ；输出功率大于２０ｍＷ；推频系数小于１００ｋＨｚ／Ｖ；可在－２０℃～＋５５℃工作。     

S波段低相位噪声参考原

阐述了研制Ｓ波段低相噪参考源所需的晶振相噪特性、倍频器相噪特性，指出研制低相噪参考源的途径，在此基础上研制出了Ｓ波段极低相噪参考源，经严格测量，其相位噪声在１ｋＨｚ处优于－１２１ｄＢｃ／Ｈｚ，１００ｋＨｚ以外的相噪平底优于－１３５ｄＢｃ／Ｈｚ。所用２０次培频器几乎无附加相噪。     

锁相介质振荡器

锁相介质振荡器采用锁柏稳频技术将介质振荡器的频率稳定在参考频率上。研制的一种Ｘ波段锁相介质振荡器,得到的性能指标如下：频率８．４４８ＧＨｚ;相位噪声≤ －８０ｄＢＣ／Ｈｚ＠１００ｋＨｚ、≤－１１０ｄＢ／Ｈｚ＠１００ｋＨｚ;输出功率≥１０ｄＢｍ;杂波≤－７５ｄＢｃ、谐波≤－３０ｄＢｃ。     

S波段频率综合技术研究

本文论述的Ｓ波段频率综合器，频率范围是２．６１￣３．９６ＧＨｚ，频率步进为２．５ＭＨｚ，相位噪声指标〈－（８８￣９３）ｄＢｃ／Ｈｚ，长期频率稳定度为１×１０＾－９／日，杂散抑制优于５５ｄＢ，谐波抑制优于５０ｄＢ，输出功率大于１４ｄＢｍ。     

低相噪音次倍频源的研制

阐述了低噪声高次倍频器的设计原理和组成部分，介绍了已研制成功的高性能低相噪Ｘ波段１００次倍频频率源，经用３０４７Ａ相噪测试系统严格孬载频为０．３ＧＨｚ、偏离载频１ｋＨｚ和１００ｋＨｚ其单边带相位噪声分别达－１０８ｄＢｃ／Ｈｚ和－１２２ｄＢｃ／Ｈｚ。分别表明，所用１００次倍频器报会加相噪，其理论值达到２０ｌｏｇＮｎＢ。     

S波段高稳锁相振荡源研究

本文阐述了用数字锁相的方法完成Ｓ波段频率源，分析了锁相环的频谱特性；并对输出信号进行了测试，其相位噪声指标￡（１０ｋＨｚ）〈－９３ｄＢｃ／Ｈｚ，杂散抑制〈－６５ｄＢｃ，输出功率大于１０ｍＷ。     

三毫米低相噪锁相系统研究

采用锁相方法，解决了三毫米波信号源的高稳定和低相噪问题，经测试，９２．６ＧＨｚ时其相位噪声指标（傅氏频率为１ＫＨｚ时），为－７５ｄＢｃ／Ｈｚ，杂散优于－５５ｄＢｃ，输出功率大于１０ｍＷ。     

Ka波段频率合成器

本文介绍了一种基于毫米波谐波混频、中频锁相的Ｋａ波段频率合成器的设计方案及实现结果。合成器的频率范围为２６．５￣４０ＧＨｚ,输出功率大于＋５ｄＢｍ,频率步进值为１ＭＨｚ,相噪指标为（１０ｋＨｚ）〈－６５ｄＢｃ／Ｈｚ,杂散低于－５５ｄＢｃ。     

A low-power integrated tuner for cable telephony applications

This paper describes an integrated tuner for cable telephony in a 0.35 /spl mu/m, 27 GHz SOI BiCMOS technology. The IC integrates a complete dual-conversion signal path including upconverter, downconverter, variable-gain amplifier, LO synthesizers with fully integrated voltage-controlled oscillators, gain control circuitry, as well as digital calibration and interface circuits. It accepts signals in the 200-880 MHz band and produces a 44 MHz IF. Drawing 168 mA from a 3 V supply, the tuner system has a worst case noise factor of 7.3 dB, system phase noise below -78 dBc/Hz at a 10 kHz offset, spurs below -42 dBc for 137 5 dBmV input channels, a gain of 60 dB, and gain control range of 68 dB. The 13 mm/sup 2/ IC meets specifications across an outdoor temperature range of -40/spl deg/C to 100/spl deg/C in production lots.     

A Quantization Noise Suppression Technique for$DeltaSigma$Fractional-$N$Frequency Synthesizers

The first circuit implementation of quantization noise suppression technique for DeltaSigma fractional- N frequency synthesizers using reduced step size of frequency dividers is presented in this paper. This technique is based on a 1/1.5 divider cell which can reduce the step size of the frequency divider to 0.5 and thus the reduced step size suppresses the quantization noise by 6 dB. This frequency synthesizer is intended for a WLAN 802.11a/WiMAX 802.16e transceiver. This chip is implemented in a 0.18-mum CMOS process and the die size is 1.23 mm times 0.83 mm. The power consumption is 47.8 mW. The in-band phase noise of -100 dBc/Hz at 10 kHz offset and out-of-band phase noise of -124 dBc/Hz at 1MHz offset are measured with a loop bandwidth of 200 kHz. The frequency resolution is less than 1 Hz and the lock time is smaller than 10 mus     

UHF RFID阅读器中低噪声Σ小数频率综合器的设计

采用0.18μmRF CMOS工艺结合EPC C1G2协议和ETSI规范要求,实现了一种应用于CMOS超高频射频识别阅读器中的低噪声ΔΣ小数频率综合器。基于三位三阶误差反馈型ΔΣ解调器,采用系数重配技术,有效提高频率综合器中频段噪声性能;关键电路VCO的设计过程中采用低压差调压器技术为VCO提供稳定偏压,提高了VCO相位噪声性能。多电源供电模式下全芯片偏置电流为9.6mA,测得在中心频率频偏200kHz、1MHz处,相处噪声分别为-108dBc/Hz和-129.8dBc/Hz。     

A 0.13μm CMOS △∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.     

基于DDS技术的X波段频率合成器

介绍了DDS的基本原理及其杂波分布,分析了影响杂波的主要因素,提出了利用DDS技术实现X波段密跳点频率合成器的方案和实验结果。此合成器的输出信号带宽1G、跳频间隔1MHz、偏离载波1kHz处的相位噪声可达105dBc/Hz、宽带杂波抑制优于60dB,具有宽带宽、低相噪、高杂波抑制,小步进等特点。     

低相位噪声微波频率源的研究

通过对微波频率源相位噪声的分析,针对一个C波段微波频率源低相位噪声的要求,对比分析了直接倍频、数字锁相以及高频鉴相之后再倍频三种方案之间的相位噪声差别。最终得出采用直接在超高频(UHF)波段对输入信号进行模拟鉴相并锁定之后再倍频才能达到所要求的相位噪声指标。对制成的样品进行了测试,取得了预期的相位噪声指标。该C波段微波频率源的相位噪声可以达到:≤-120 dBc/Hz@1 kHz,≤-125 dBc/Hz@10 kHz,≤-130dBc/Hz@100kHz,≤-140 dBc/Hz@1 MHz。直接在UHF波段进行高频鉴相的技术,通过提高鉴相频率大幅降低了微波锁相频率源的相位噪声。     

V波段小型化低相噪频率综合器

本文研究了一种V波段超小型低相噪频率综合器,研制了L段捷变频频综、Ku波段取样锁相源、上变频组件、倍频器等四个小型化组件.为了得到较低的相位噪声和捷变频速度,本捷变频频综采用上变频-倍频方案,其中DRO PLS保证低相位噪声性能,L波段捷变频频综保证捷变频功能.该频综尺寸为100×80×30mm³,相位噪声低于-86dBc/Hz(1kHz),捷变频时间小于40μs,杂波抑制优于-60dBc.     

全集成低噪声CMOS宽带分数分频频率综合器

设计了一款应用于CMMB数字电视广播接收的全集成低噪声宽带频率综合器。采用三阶ΣΔ调制器小数分频器完成高精度的频率输出,使用仅一个低相位噪声的宽带VCO输出频率范围覆盖900~1 600 MHz,产生的本振信号覆盖UHF的数字电视频段(470~790 MHz)。设计中的频率综合器能在所有的频道下保证环路的稳定以及最小的环路性能偏差。测试结果表明,整个频率综合器的带内相位噪声小于-85 dBc/Hz,并且带外相位噪声在1MHz时均小于-121 dBc/Hz,总的频率综合器锁定时间小于300μs。设计在UMC 0.18μm RFCMOS工艺下实现,芯片面积小于0.6 mm2,在1.8 V电源电压的测试条件下,总功耗小于22 mW。     

低相噪硅雷达射频频率源的研究与设计

分析了频率源中各个模块的噪声传递函数,确定影响近端噪声的模块分别是鉴频鉴相器-电荷泵(PFD-CP)、分频器;在默认分频器相位噪声为-158dBc/Hz,通过matlab建模推断,需要PFD-CP模块在10kHz频偏处的输入噪声达到-143dBc/Hz,才能实现频率源输出信号在10kHz频偏处相位噪声-107dBc/Hz。采用0.18μmSiGe BiCMOS工艺,设计了整块芯片,着重优化了PFD-CP模块的输入噪声,经过spectre仿真,PFD-CP模块的输入噪声为-146dBc/Hz,经过实测,输出信号在10kHz频偏处相位噪声为-108dBc/Hz,达到设计预期。     

A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy

Injection-locked quadrature voltage-controlled oscillators are introduced in this paper as high accuracy, low phase noise, and low-power I and Q generators. A master voltage-controlled oscillator (VCO), running at twice the output frequency, locks two coupled VCOs. The former determines phase noise while the latter sets phase accuracy, thus, breaking the tradeoff between the two parameters, the main limit of free running coupled VCOs, recently proposed in the framework of highly integrated solutions. The proposed design has been tailored to DCS 1800 and prototypes have been fabricated in a 0.18-/spl mu/m CMOS technology. Experiments show a phase noise of -127 dBc/Hz and -139 dBc/Hz at 600 kHz and 3 MHz, respectively, while consuming 10 mA from 1.8 V supply. A 185-dB state-of-the-art phase noise figure of merit results. Accuracy between output signals is determined by means of image band rejection (IBR) measurements on a purposely developed single-side-band upconversion mixer. Minimum IBR among 20 samples is as large as 46 dB.