Thermomechanical response and stress analysis of copper interconnects

This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability issues for modern copper/low-k dielectric interconnect systems are discussed.     

Improved compact thermal model for studying 3-D interconnect structures with low-k dielectrics

Compact thermal modeling is gaining significance as interconnect feature sizes continue to shrink, requiring increased computation times for full-field multi-scale simulations. Improved and expanded uses of an existing compact thermal modeling approach found in Gurrum et al. [A compact approach to on-chip interconnect heat conduction modeling using the finite element method, ASME J. Electron. Packaging (2007), accepted], Gurrum et al. [A novel compact method for thermal modeling of on-chip interconnects based on the finite element method, ASME, EEP 3, Electron. Photon. Packing Electr. Syst. Photon. Des. Nanotechnol. (2003) 441-445] are presented here. The first improvement rectifies a singularity that occurs in the previous compact model. This change allows for greater flexibility in mesh application, and a greater number of structures that can be analyzed. This work focuses on the application of the compact thermal model to two interconnect structures. The first geometry [S. Im, N. Srivastava, K. Banerjee, K. Goodson, Scaling analysis of multilevel interconnect temperatures for high performance ICS, IEEE Trans. Electron. Dev. 52 (12) (2005) 2710-2719] is a typical interconnect structure based on the ITRS 65 nm technology node. A new transient compact model was applied to another geometry [J. Zhang, M. Bloomfield, J. Lu, R. Gutmann, T. Cale, Thermal stresses in 3D IC inter-wafer interconnects, Microelectron. Eng. 82 (3-4) (2005) 534-547], which is a more advanced technology with a through-the-die via structure. The second improvement of the compact model is extending the steady state finite element based model into a transient version. Full-field simulations have very large storage and memory requirements for transient analysis of complex structures. The advantage of this compact model is that in addition to increased efficiency, the methodology and implementation is similar to a traditional finite element analysis (FEA).     

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.     

Thermo-mechanical stresses in copper interconnects - A modeling analysis

This study focuses on numerical modeling of thermo-mechanical stresses in copper interconnects. The three-dimensional analyses utilize a two-level metal structure connected by a via. Attention is devoted to the effects of the incorporation of polymer-based low-k dielectric material. Deformation is generated by thermal strain mismatches during cooling from an elevated temperature, as well as from cyclic thermal excursions. The thin barrier layers encasing the copper are also included in the models. Plastic deformation in the metal is taken into consideration in the analysis. The stress and deformation fields are examined in detail. It is found that the incorporation of low-k dielectric in place of traditional oxide-based dielectric significantly reduces the triaxial tensile stresses in copper but enhances plastic deformation, particularly in the via and its vicinity. The generation of shear stresses at the interface regions is also assessed. A parametric analysis is conducted to elucidate the individual influences of the thermal expansion and elastic properties of the dielectric material. Salient features having direct implications in device reliability are highlighted and discussed.     

空气隙Cu互连结构热应力史研究

将空气引入Cu导线间形成空气隙,可有效降低等效介电常数K_(eff),但同时也使互连结构的机械稳定性面临着挑战。利用ANSYS进行了有限元热分析,研究了制备空气隙Cu互连结构的两种主流工艺过程,即CVD沉积法和热分解牺牲层法,模拟了Cu导线上的热应力变化趋势,并比较了两者的优劣,最终发现互连结构经过一系列热应力的循环作用后,各种材料在不同程度上都有较大的形变,这将影响结构的机械稳定性,甚至引起破坏。所以,需要进一步改善结构设计和使用理想电介质。     

Direct sub-100-nm patterning of an organic low-k dielectric for electrical and optical interconnects

Low-k dielectric materials compatible with copper interconnect fabrication processes extending to the sub-50-nm technology nodes are desired for high speed integrated circuit (IC) fabrication. We demonstrate that bisbenzocyclobutene (BCB), an organic low-k dielectric material, can be patterned with sub-100-nm resolution using electron beam lithography, providing new avenues for nanoscale electrical and optical interconnect fabrication.     

Structure and property characterization of low-k dielectric porous thin films

A novel methodology is developed that uses a combination of high energy ion scattering, x-ray reflectivity, and small angle neutron scattering to characterize the structure and properties of porous thin films. Ion scattering is used to determine the elemental composition of the film for absolute intensity calibration of the x-ray and neutron scattering techniques. X-ray reflectivity is used to measure the average electron density and film thickness. Small angle neutron scattering is used to determine the pore size, structure, and connectivity. Combining information from all three techniques, the film porosity and matrax material density can be uniquely determined.     

Study of ultrathin vanadium nitride as diffusion barrier for copper interconnect

Ultrathin Vanadium nitride (VN) thin film with thickness around 10 nm was studied as diffusion barrier between copper and SiO₂ or Si substrate. The VN film was prepared by reactive ion beam sputtering. X-ray diffraction, Auger electron spectroscopy, scanning electron microscopy and current-voltage (I-V) technique were applied to characterize the diffusion barrier properties for VN in Cu/VN/Si and Cu/VN/SiO₂ structures. The as-deposited VN film was amorphous and could be thermal stable up to 800 °C annealing. Multiple results show that the ultrathin VN film has good diffusion barrier properties for copper.     

Deformation and interfacial sliding in back-end interconnect structures in microelectronic devices

Deformation of interconnect structures at the back-end of microelectronic devices during processing or service can have a pronounced effect on component reliability. Here, we use atomic force microscopy (AFM) to study plastic deformation and interfacial sliding of Cu interconnects on Si. The behavior of both standalone Cu lines and lines embedded in a low-K dielectric (LKD) was studied. Following thermal cycling, changes were observed in the in-plane (IP) Cu line dimensions, as well as the out-of-plane (OOP) step height between Cu and the dielectric in single-layer structures. These were attributed to differential deformation of the Cu/Si and Cu/dielectric material pairs caused by thermal expansion mismatch, accommodated by interfacial creep. These results are discussed in light of previous work on the mechanism of interfacial creep. A simple shear-lag-based model, which may be used to estimate the extent of interfacial sliding, is proposed. Some experimental results on the distortion of Cu lines caused by package-level stresses following thermal cycling are also presented.     

Advanced metrology for rapid characterization of the thermal mechanical properties of low-k dielectric and copper thin films

Evaluation of the thermal mechanical properties of new materials like Cu and low-krequire multiple complementary metrology toolsets. We report two complementary metrology tools that have a potential to rapidly screen new materials through the integration process. The first is an in-situ integrated metrology chamber that simultaneously measures several physical, optical, chemical, and electrical changes during a heat cycle. Complementing these measurements with results from quantitative adhesion testing, based on the modified edge lift off test (MELT) principle, the thermal mechanical properties of new materials can be rapidly screened and evaluated.     

Evaluation of ultra-low-k dielectric materials for advanced interconnects

The International Technology Roadmap for Semiconductors predicts that continued scaling of devices will require ultra-low-k materials with k values less than 2.5 for the 100 nm technology node and beyond. Incorporation of porosity into dense dielectrics is an attractive way to obtain ultra-low-k materials. Electrical and physical properties of ultra-low-k materials have been characterized. Integration evaluations showed both feasibility and challenges of porous ultra-low-k materials. This paper discusses issues and recent progress made with porous ultra-low-k material properties, deposition processes, characterization metrologies, and process integration.     

低k介质与铜互连集成工艺

阐明了低k介质与铜互连集成工艺取代传统铝工艺在集成电路制造中所发挥的关键作用。依照工艺流程,介绍了如何具体实现IC制造多层互连工艺:嵌入式工艺、低k介质与平坦化、铜电镀工艺与平坦化;阐述了工艺应用现况与存在的难题,给出了国际上较先进的解决方法。     

Characterization and impact of reduced copper plating overburden on 45 nm interconnect performances

During first metal level interconnects fabrication, a controlled modification of the electro-deposited copper over-deposition (overburden) is performed using a partial chemical-mechanical polishing (CMP) step. Next, copper microstructure is stabilized with a short duration hot-plate anneal. Overburden is then removed during CMP end-of-step. Ionic microscopy and EBSD observations of overburden thickness reduction reveal that copper grain growth occurs differently, according to patterned geometries and with a strong 〈1 1 1〉 texture, as observed in modified films. Reduction of overburden thickness also reveals the capacity of anneal temperature to impact electrical performances. Reliability is impacted for thinnest wires.     

Cu CMP工艺对薄膜介电常数的影响机制

研究了使用不同研磨液的Cu CMP工艺对超低介电常数(ULK)薄膜介电常数k值的影响.实验结果表明经过Cu CMP工艺,ULK薄膜的介电常数k均有不同程度的增加.XPS成分分析结果表明,ULK薄膜表面C含量的增加是造成介电常数k值升高的主要原因.这主要是由于CMP工艺中,化学品溶液进入多孔的ULK薄膜.而退火工艺可以使得化学品挥发,从而使ULK薄膜表面C含量降低,由此介电常数k基本上得以恢复.初步建立了Cu CMP工艺对介电常数k影响的物理模型.根据模型计算的k结果为2.75,与实测值2.8基本符合.     

Microstructural characterization of inlaid copper interconnect lines

The microstructure of inlaid Cu lines has been quantified as a function of annealing conditions, post-plating, and post-CMP. The grain size distribution was measured using the median intercept method, crystallographic texture was characterized by pole figure analysis, and mechanical stress was determined using x-ray diffraction. The median grain size and mechanical stress level increase with increasing anneal temperature. The crystallographic texture is independent of the anneal temperature and is predominantly (111) with a small fraction of sidewall-nucleated (111) grains. The (111) grains nucleated from the trench bottom have a preferred in-plane orientation. The grain growth in the trench is independent of that in the overburden.     

Electromigration in sputtered copper film on plasma-treated hydrogen silsesquioxane dielectric

Electromigration (EM) damage is one of the major causes for the failure of interconnects. Plasma treatment, such as dry etching, is frequently employed in the fabrication of multilevel interconnection patterns. This work investigates the hydrogen silsesquioxane (HSQ) and copper integrated systems and the effect of H₂ plasma treatment on the EM of Cu. Hydrogen plasma bombardment induces a rough HSQ surface and results in a coarse morphology of the Cu film deposited on HSQ. The crystallographic texture of Cu is also affected by the plasma treatment. A decrease in the Cu I(111)/I(200) peak ratio is observed for a specimen treated with H₂ plasma. The activation energy for EM in Cu and the EM lifetime of the Cu interconnect decreases with an increased degree of plasma treatment. The activation energies obtained, ranging from 0.76 eV to 0.94 eV, suggest that the electromigration in copper proceeds via an interfacial diffusion path. Possible mechanisms for the effects of plasma treatment are explored. The rough surface and the retarded Cu (111) orientation induced by H₂ plasma bombardment are the major causes for the decrease of activation energy and EM lifetime.     

添加剂对铜互连线脉冲电镀的影响

目前,铜互连技术已成为超大规模集成电路的主流互连技术,铜的填充主要采用Damascene工艺进行电镀。有机添加剂一般包括加速剂、抑制剂和平坦剂,它们在电镀液中含量虽然很少,但对于铜电镀的过程非常关键。以Enthone公司的ViaForm系列添加剂为例,研究了每种类型添加剂对脉冲铜镀层性能的影响。     

FCCL高频介电性能和介电热系数的测量

由于FCCL机械性能特点,FCCL大量用于刚挠结合电路。而应用在FCCL电路的传输频率较低,高频介电性能如介电常数Dk和介电损耗角正切Df未被重视起来。本文利用分离式介质谐振腔法测量FCCL的介电性能,测试频率范围为1.1 GHz~15.5 GHz,并测量其介电常数热系数TCEr。     

Temperature and duration effects on microstructure evolution during copper wafer bonding

Interfacial morphologies during Cu wafer bonding at bonding temperatures of 300–400°C for 30 min followed by an optional 30-min or 60-min nitrogen anneal were investigated by means of transmission electron microscopy (TEM). Results showed that increased bonding temperature or increased annealing duration improved the bonding quality. Wafers bonded at 400°C for 30 min followed by nitrogen annealing at 400°C for 30 min, and wafers bonded at 350°C for 30 min followed by nitrogen annealing at 350°C for 60 min achieve the same excellent bonding quality.     

CSP结构的热应力分析

利用ansys软件通过仿真得到了在稳态情况下的CSP结构热场分布,在此基础上,把稳态情况下的热场分布作为温度载荷施加到模型上,得到了CSP结构热应力分布,这对集成电路热设计方案的选择,尤其对提高大功率集成电路的可靠性具有重要意义.