The origin of the kink phenomenon of transistor scatteringparameter S22

A novel theory based on dual-feedback circuit methodology is proposed to explain the kink phenomenon of transistor scattering parameter S₂₂. Our results show that the output impedance of all transistors intrinsically shows a series RC circuit at low frequencies and a parallel RC circuit at high frequencies. It is this inherent ambivalent characteristic of the output impedance that causes the appearance of kink phenomenon of S₂₂ in a Smith chart. It was found that an increase of transistor transconductance enhances the kink effect while an increase of drain-to-source (or collector-to-emitter) capacitance obscures it. This explains why it is much easier to see the kink phenomenon in bipolar transistors, especially heterojunction bipolar transistors, rather than in field-effect transistors (FETs). It also explains why the kink phenomenon is seen in larger size FETs and not in smaller size FETs. Our model not only can predict the behavior of S₂₂, but also calculate all S-parameters accurately. Experimental data of submicrometer gate Si MOSFETs and GaAs FETs are used to verify our theory. A simple method for extracting transistor equivalent-circuit parameters from measured S-parameters is also proposed based on our theory. Compared with traditional Z- or Y-parameter methods, our theory shows another advantage of giving deep insight into the physical meaning of S-parameters     

RF performance of diamond MISFETs

A cutoff frequency (f_T) of 11 GHz is realized in the hydrogen-terminated surface channel diamond metal-insulator-semiconductor field-effect transistor (MISFET) with 0.7 μm gate length. This value is five times higher than that of 2 μm gate metal-semiconductor (MES) FETs and the maximum value in diamond FETs at present. Utilizing CaF₂ as an insulator in the MIS structure, the gate-source capacitance is reduced to half that of the diamond MESFET because of the gate insulator capacitance being in series to the surface-channel capacitance. This FET also exhibits the highest f _max of 18 GHz and 15 dB of power gain at 2 GHz. The high-frequency equivalent circuits of diamond MISFET are deduced from the S-parameters obtained from RF measurement     

An analytic method to determine GaAs FET parasitic inductances anddrain resistance under active bias conditions

An analytic technique to determine the parasitic inductances, source resistance, and drain resistance of the FET equivalent circuit is presented in this paper. The method exploits the frequency dependence of the extracted circuit parameters to determine the parasitic inductances and drain resistance from S-parameters measured over frequency for one active bias condition. Given a value for the parasitic gate resistance R _g, all of the other equivalent-circuit parameters are uniquely extracted. The method is fast and robust, making it suitable for in-line statistical process tracking, as well as device modeling. A process tracking example for a 12-wafer 1864-device sample and FET modeling results up to 40 GHz are also presented     

Accurate small-signal modeling of HFET's for millimeter-waveapplications

In this paper we discuss the small-signal modeling of HFET's at millimeter-wave frequencies. A new and iterative method is used to extract the parasitic components. This method allows calculation of a π-network to model the heterojunction field-effect transistor (HFET) pads, thus extending the validity of the model to higher frequencies. Formulas are derived to translate this π-network into a transmission line. A new and general cold field-effect transistor (FET) equivalent circuit, including a Schottky series resistance, is used to extract the parasitic resistances and inductances. Finally, a new and compact set of analytical equations for calculation of the intrinsic parameters is presented. The real part of Y₁₂ is accounted for in these equations and its modeling is discussed. The accounting of Re(Y₁₂ ) improves the S-parameter modeling. Model parameters are extracted for an InAlAs/InGaAs/InP HFET from measured S-parameters up to 50 GHz, and the validity of the model is evaluated by comparison with measured data at 75-110 GHz     

A new extraction method to determine bias-dependent source seriesresistance in GaAs FET's

A new method is proposed to determine bias-dependent source resistances for GaAs field-effect transistors (FET's). This method, which is a cold-FET measurement technique, utilizes the relations between the real part of the two-port impedances transformed from the measured S-parameters and their algebraic derivatives. It is based on the fact that the algebraic derivatives of the two-port resistances result in the simple form at the normal cold-FET condition. A bias-independent gate resistance is extracted at the pinched-off cold-FET condition to fulfill necessary and sufficient conditions in extraction. The proposed method is a direct measurement because only algebraic calculation is required, and it is general enough to need only one assumption of the laterally symmetric channel-doping profile. The deleterious results of dispersion (frequency dependence) and negative value in source resistances at the pinched-off cold-FET condition are explained by the effects of the leakage current and the on-wafer pad parasitics, respectively. The problem of deviation of α₂₁ and α₁₂ from 0.5 at the normal cold-FET condition is also resolved by deembedding the on-wafer pad parasitics. This method allows one to extract bias-dependent source resistances for GaAs FET's     

Characterization of finite-ground CPW reactive series-connectedelements for innovative design of uniplanar M(H)MICs

A variety of finite-ground coplanar waveguide (FGCPW) reactive series-connected capacitive and inductive elements are extensively studied and characterized as equivalent-circuit models that include complex parasitic effects caused by finite-ground widths. These models are developed by implementing a numerical calibration procedure called short-open calibration, which is used to extract characteristic parameters of the circuit model from full-wave method-of-moments calculations. The proposed model is generally described as an equivalent series admittance (Y_g) or impedance (Z_g) together with a pair of shunt admittances (Y_p) for FGCPW series-connected structures. With the new scheme, the FGCPW elements of interest behave like lossless lumped elements at low-frequency range, consisting of a series capacitance or inductance, as well as two shunt capacitances. As frequency increases, however, Y_g and Z_g exhibit a frequency-related dispersion and also a lossy resonance behavior, which stand for some added inductive or capacitive coupling effect caused by the extent of finite-ground width. On the other hand, unbounded radiation effect, considered in this model, appears too strong to be ignored around resonance. Theoretical and experimental results that compare very well with each other are shown for interesting electrical behaviors of finite-ground structures. An innovative uniplanar three-stage bandstop filter is designed and measured on the basis of its simplified equivalent-circuit model     

Polarization Engineering on Buffer Layer in GaN-Based Heterojunction FETs

To improve the pinched-off characteristics of an AlGaN/GaN heterojunction field effect transistor (HJFET), the conduction band potential of an incorporated AL_xGa_1-xN buffer is designed to be upwardly convex in a band diagram. This approach utilizes the polarization effects specific to GaN-based materials by lowering the Al content x from 30% to 5% almost linearly toward the front side. Fabricated field effect transistors (FETs) adopting the designed buffer have demonstrated the following advanced characteristics in comparison to those of a FET adopting a conventional GaN buffer: less than one-tenth of the buffer leakage current, a gate-to-drain breakdown voltage BV_gd twice or more as high, and remarkably improved carrier confinement and pinched-off behavior. The FETs are operated in an enhancement mode with a gate-to-channel distance thick enough to prevent tunneling current through the gate.     

Measurement-based closed-form modeling of surface-mounted RF components

An understanding of the parasitic and packaging effects of passive surface-mounted devices (SMDs), including characterization of the pertinent interconnects, is required for developing robust equivalent-circuit models that are useful in RF and microwave computer-aided design. In this paper, we develop a procedure for modeling SMD inductors and capacitors, which incorporates the nonideal behavior associated with frequency dispersion, board layout, component parasitics, and device packaging. The equivalent-circuit parameters are extracted in closed-form from accurate in-situ measurement of the component's S-parameters, without the necessity for cumbersome optimization procedures normally followed in RF equivalent-circuit synthesis.     

Small-signal characteristics of n+-Ge gate AlGaAs/GaAsMISFET's

The small-signal characteristics have been clarified by S-parameter measurements and equivalent circuit modeling. A large intrinsic transconductance of 630 mS/mm and a maximum cutoff frequence f_T of 70 GHz have been achieved for a MISFET with a gate length of 0.4 μm. The average electron drift velocity in the channel, evaluated from the f_T, was as high as 1.7×10⁷ cm/s. In obtaining an equivalent-circuit model, a gate conductance parallel to the gate-source capacitance is introduced to take into account the gate forward current of normally-off FETs The gate conductance does not cause the f _T of the MISFET to deteriorate due to a small gate forward current at a large gate bias, in contrast to GaAs MESFETs     

A new technique to extract channel mobility in submicron MOSFETsusing inversion charge slope obtained from measured S-parameters

We present a novel method to extract the effective channel mobility directly from measured S-parameters in submicron MOSFETs. This method is based on the slope extraction of the total gate charge versus mask gate length from measured S-parameters. Unlike conventional approaches, the use of a very long channel test device or the extraction of the parasitic capacitance and effective channel length are not required to extract the mobility in short-channel LDD devices, thus making the new method more accurate and simpler. The validity of the method is demonstrated by comparing the result with those using a previously reported method     

一种基于半分析法的HEMT小信号参数的提取方法

提出了一种基于半分析法的高速电子迁移率半导体晶体管小信号模型的提取方法.此方法是用测试结构的方法来提取焊盘电容和寄生电感,半分析法来提取寄生电阻,提高了寄生电阻的提取精度.在频率高达40 GHz的范围内,多偏置情况下模拟的S参数和测试的S参数曲线吻合良好,证明这种方法是正确的.     

Direct parameter-extraction method for HBT small-signal model

An accurate and broadband method for the direct extraction of heterojunction bipolar transistor (HBT) small-signal model parameters is presented in this paper. This method differs from previous ones by extracting the equivalent-circuit parameters without using special test structures or global numerical optimization techniques. The main advantage of this method is that a unique and physically meaningful set of intrinsic parameters is extracted from the measured S-parameters for the whole frequency range of operation. The extraction procedure uses a set of closed-form expressions derived without any approximation. An equivalent circuit for the HBT under a forward-bias condition is proposed for extraction of access resistances and parasitic inductances. An experimental validation on a GaInP/GaAs HBT device with a 2×25 μm emitter was carried out, and excellent results were obtained up to 30 GHz. The calculated data-fitting residual error for three different bias points over 1-30 GHz was less then 2%     

Extremely low-noise performance of GaAs MESFETs with wide-headT-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-μm Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L_h) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anhold's method. A current gain cutoff frequency (f_T) and a maximum stable gain (MSG) decrease monotonously as L_h increases on account of parasitic capacitance. However, the device with L_h of 1.0 μm, which has lower gate resistance than 1.0 Ω, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMT's     

New GaAs-MMIC process technology using low-temperature depositedSrTiO3 thin film capacitors

The authors have developed a new GaAs-MMIC process technology using low-temperature deposited SrTiO₃ thin film capacitors which were combined with WSi-gate selfaligned FETs. The SrTiO₃ films were successfully deposited at 200°C by the RF magnetron sputtering method without degrading the FET characteristics. By integrating these on-chip SrTiO₃ bypass capacitors onto the GaAs IC, the parasitic inductance from the source to ground interconnection was successfully reduced and an enhanced gain characteristic was obtained for a self-biased amplifier circuit     

High power DPDT antenna switch MMIC for digital cellular systems

In this paper, we propose two new types of dual-pole double-throw (DPDT) switch GaAs JFET monolithic microwave integrated circuits (MMICs) for digital cellular handsets. These ICs have the excellent characteristics of low insertion loss and high power handling capability, even with a low control voltage by stacking three JFETs with shallow V_p and using a novel bias circuit using p-n junction diodes. One DPDT switch IC has two shunt FET blocks and can achieve high isolation without external parts. An insertion loss less than 0.6 dB and isolation over 25 dB up to 2 GHz were achieved. P_1dB was about 35 dBm even with a control voltage of 0/3 V. Another DPDT switch IC utilizes parallel resonance of external inductors and parasitic capacitance between the drain and the source of the OFF-state FETs. By attaching 15 nH inductors, for example, the IC exhibited an insertion loss as low as 0.4 dB, an isolation of better than 40 dB at 1.5 GHz, a bandwidth of about 400 MHz for 20 dB isolation, and P_1dB of about 34 dBm with the 0/3 V control     

A pure analytic method for direct extraction of collector-up HBT's small-signal parameters

A pure analytic procedure for direct extraction of the small-signal equivalent-circuit parameters, including extrinsic inductances, has been demonstrated and successfully applied to III-V and SiGe collector-up heterojunction bipolar transistors (HBTs). This method can alleviate some difficulties encountered among conventional extracting techniques that are the use of additional test structures, forward-biased measurements at specific bias conditions, and empirical optimization process. In this paper, the hybrid-/spl pi/ equivalent-circuit elements are extracted in a simple and efficient way from impedance and admittance formulation on the basis of measured S-parameters. To study the bias dependence, the extrinsic and intrinsic circuit components are evaluated under different bias conditions. The model parameters are sequentially derived during the extraction process yielding a full set of physical element values. The validity of our model is explored on pnp collector-up AlGaAs-InGaAs HBTs, and a good coincidence between measured and modeled S-parameters is observed for the entire frequency range of operation. Consistent extracted trends indicate that this improved equivalent-circuit model is suitable to be implemented in circuit simulators for microwave-circuit TCAD applications.     

A simplified procedure to calculate the power gain definitions ofFETs

A graphical method to easily derive the power gain definitions of field-effect transistors (FETs) is proposed in this paper. This method is applicable to MESFETs and high electron-mobility transistors described by the typical π model. A new set of simple expressions of the S-parameters, functions of the circuit elements of the FET complete model, is derived. These expressions are presented in graphic form to quickly compute the modules of the FET S-parameters and then the power gains. The accuracy of this approach has been proven by comparison with simulations of the FET complete model     

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C_gb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I_dsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g_m) degradation and, eventually, cutoff frequency (f_T) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f_T is largely affected by local stress change, i.e., g_m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f_T is dominated by increased parasitic capacitance (C_gb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f_T has been observed through layout optimization for C_gb reduction by increasing the transistor active-to-SC spacing.     

A novel, bias-dependent, small-signal model of the dual-gate MESFET

A dual-gate MESFET from NEC (NE25000) has been measured and modeled. S-parameters and drain-to-source currents calculated from the model are in good agreement with measured data. The model consists of a cascode of two intrinsic, single-gate, nonlinear FET-models embedded in a network representing the device parasitics. A step-by-step procedure has been used to determine the 47 parameters of the model. DC-measurements were used to find starting values for some of the parameters of the nonlinear models. The parasitic capacitances were determined from three-port S-parameters measured at V_DS=0 V, I_DS=0 A and V(G₁S)=V(G₂S)=-4.0V. The parasitic inductances and resistances were determined from S-parameters measured at the same bias-point but with forward-biased gates, and from DC-measurements. The final model-optimization was done by simultaneously fitting the model to drain-to-source currents and three-port S-parameters measured at several different, active bias-points (V_DS >0)     

A self-backgating GaAs MESFET model for low-frequency anomalies

A self-backgating GaAs MESFET model which can simulate low-frequency anomalies has been developed by including deep-level trap effects. These cause transconductance reduction due to electron emission from EL2 in the depletion width change at the edge of the Schottky gate junction and the output conductance to increase due to the time-dependent net negative charge concentration in the semi-insulating substrate as a result of self-backgating with the applied signal frequency. This model has been incorporated in PSPICE and includes a time-dependent I-V curve model, a capacitance model, an RC network describing the effective substrate-induced capacitance and resistance, and a switching resistance providing device symmetry. An analytical capacitance model describes the dependence of capacitance on V_gs and V_ds and includes the channel-substrate junction modulation by the self-backgating effect. A transit-time delay is also included in the transconductances, g_m and g_mbs, for model accuracy and to describe the phase shift of S-parameters. Measured data correspond to simulations by this model of the low-frequency anomalous characteristics, voltage-dependent capacitances, and S-parameters of conventional GaAs MESFETs for linear and microwave circuit design