A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

We describe a DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies. It utilizes simultaneous bidirectional (SBD) signaling in a daisy-chained (repeated), point-to-point configuration to enable high performance scalable memory subsystems; and also provides direct attach capability for DRAMs to memory controllers or other logic devices. Source-synchronous strobes are used for data capture, minimizing strobe-to-data jitter. A low-jitter differential clock retimes the data at each DRAM on a per DIMM basis preventing jitter from accumulating in repeated data. The phase of this clock is adjusted on each DRAM to minimize the latency of the repeaters. 80 mW of total power is dissipated per DRAM I/O at 3.6 Gb/s. We present results from a system using both memory controller and DRAM repeater test chips.     

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifier at 500 MHz. The fully AC coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-/spl mu/m 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330/spl times/85 /spl mu/m/sup 2/.     

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

This paper describes a 144-Mb DRAM that operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121-mm/sup 2/ die is fabricated in a 0.13-/spl mu/m logic-based process with embedded DRAM. The cycle time is achieved using an early-write sensing technique that eliminates most of the timing overhead associated with the write cycle. Dynamic-precharge decoding in the subarray decode path is implemented to improve the access time. An improved data-formatting circuit is used to arrange the exit order of the eight-word burst. These circuit techniques produce latencies of 5.0 ns. The DRAM uses a DDR3-SRAM interface and is function and package compatible with industry-standard DDR3 SRAMs. Highlights of the DDR3 interface include the use of active termination circuitry on all inputs. The active termination improves the data-eye window and improves data capturing with minimum data setup and hold.     

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext.     

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fibercommunication systems using n-AlGaAs/i-InGaAs HJFET's

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-μm GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V     

A 500-Mb/s quadruple data rate SDRAM interface using a skewcancellation technique

A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required. A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-μm CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply. The active die area of the chip with the on-chip data pattern generator is 2.4 mm²     

Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond

The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 10 Gb/s, including 10 GB Ethernet (GBE, 10 Gb/s, or 4 $,times,$10.3125 Gb/s, and 10$,times,$10.3125 Gb/s for Ethernet 40 G/100 G), 8$,times$ fibre channel (8.5 Gb/s), and PCI Express Gen 3 (at 8 Gb/s). At those data rates, the total available timing budget become less, data-dependent jitter gets severe, and jitter amplification becomes significant. This paper focuses on these jitter challenges and associated mitigation/reduction technologies, including jitter tracking via clock recovery, eye-opening via equalizations, and DCD cancellation via delay elements to avoid jitter amplification.      

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 33.6–33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 $^{11} -$1 PRBS. The measured bit error rate is less than $10^{-8}$ for a 33.72 Gb/s, 2$^{7} -$1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.      

A CMOS 10-gb/s power-efficient 4-PAM transmitter

A novel power-efficient architecture for a multilevel pulse amplitude modulation (PAM) transmitter is proposed. A data-look-ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. This technique also eliminates the need for a pre-driver block, which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18-/spl mu/m standard digital CMOS technology. The transmitter achieves 3.5 GS/s (7 Gb/s) with a 1.7-V supply and 5 GS/s (10 Gb/s) with a 2-V supply and it occupies an area of 0.16 mm/sup 2/. The output driver and the entire transmitter consume only 11.25 and 66 mW at 7 Gb/s (20 and 121 mW at 10 Gb/s), respectively, which are the lowest reported powers at this speed.     

A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μmSOI-CMOS technology

This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

A 27-mW 3.6-gb/s I/O transceiver

This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.     

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 /spl mu/m CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.     

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-/spl mu/m, 2-metal layers DRAM process, and the active area is 330 /spl times/ 66 /spl mu/m/sup 2/. It exhibits 200 mV /spl times/ 690 ps eye windows on the given channel with a 1.8-V supply voltage.     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery

This paper presents a 40 Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high- and low-frequency contents of the signal. A full-rate bang-bang phase detector with only five latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors. The performance is also improved by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40 Gb/s data passing through a 4 m cable with 10 dB loss at 20 GHz. For an input PRBS of 2 $^{7}-$1, the recovered clock jitter is 0.3 ps$_{rm rms}$ and 4.3 ps$_{rm pp}$. The retimed data exhibits 500 mV $_{rm pp}$ output swing and 9.6 ps$_{rm pp}$ jitter with ${hbox{BER}}≪ 10^{-12}$ . Fabricated in 90 nm CMOS technology, the receiver consumes 115 mW , of which 58 mW is dissipated in the equalizer and 57 mW in the CDR.      

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2$times$-oversampling phase-tracking CDR, implemented in 90$,$nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of ${pm }{hbox{615~ppm}}$ between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate ${≪} hbox{10}^{-12}$ was verified up to 38 Gb/s using a 2$ ^{7} -$1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90$~$nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 ${hbox{mm}}^{2}$ .      

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications

A 12-GS/s 8-bit digital-to-analog converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350 mum and achieves INL and DNL of 0.31 and 0.28LSB, respectively. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. Measured SDR and 3-dB bandwidth using 12 GS/s random data are 32 dB and 7.1 GHz, respectively. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.