一款高性能共源共栅运算放大器设计

基于CSMC 0.5μm标准CMOS工艺,采用复用型折叠式共源共栅结构,设计一种折叠式共源共栅运算放大器。该电路在5V电源电压下驱动5pF负载电容,采用Cadence公司的模拟仿真工具Spectre对电路进行仿真。结果表明,电路开环增益达到了71.7dB,单位增益带宽为52.79MHz,开环相位裕度为60.45°。     

High-drive CMOS current amplifier

A high-performance current amplifier is proposed which is based on a folded-cascode transresistance amplifier and a low-distortion class AB current output stage. The loop gain of the transresistance amplifier exhibits a gain bandwidth product of 10 MHz and a DC gain as high as 100 dB which allows accurate closed-loop operations to be achieved. Despite the intrinsic low-linearity performance of current amplifiers with respect to their voltage amplifier counterpart, the proposed circuit provides an output current of 7 mA with a total harmonic distortion (THD) better than -55 dB while requiring only 200 μA of quiescent current for the output transistors. The circuit was fabricated in a 1.2 μm CMOS process, uses a 5 V power supply, and dissipates 4 mW     

A wideband high-CMRR single-ended to differential converter

A novel circuit topology that provides wideband single-ended to differential conversion is presented. The proposed circuit exploits a negative feedback loop to generate a second input signal for a differential pair, thus obtaining 6 dB extra conversion gain and higher CMRR with respect to a simple differential pair driven single-ended. A signal and noise model for the circuit is proposed, based on admittance parameters and the use of a novel analysis technique to open the feedback loop while maintaining closed loop loading effects. The model is exploited to derive design guidelines in bipolar and MOS technologies. Measurements on a test chip in STMicroelectronics BiCMOS7 technology are reported to compare the performance of the proposed topology and of a simple differential pair used as single-ended to differential converter.     

高性能折叠式共源共栅运算放大器的设计

折叠式共源共栅结构能够提供足够高的增益,并且能够增大带宽、提高共模抑制比和电源电压抑制比.基于Chartered 0.35 μm工艺,设计了一种折叠式共源共栅结构的差分输入运算放大器,给出了整个电路结构.Spectre仿真结果表明,该电路在3.3V电源电压下直流开环增益为121.5dB、单位增益带宽为12 MHz、相位裕度为61.4°、共模抑制比为130.1dB、电源电压抑制比为105 dB,达到了预期的设计目标.     

一种降低高频噪声的前置全差分运算放大器

提出了一种降低高频噪声的前置全差分放大器.运放内部采用了两组偏置电路,一组用于单位增益缓冲器电路,一组用于放大电路.为了确保电路稳定性又不增加设计难度,将单位增益缓冲器电路与共模反馈回路结合起来.设计采用HHNEC 0.18μm BCD工艺,Cadence Spectre仿真表明,正常工作时共模反馈的环路增益84.93dB,单位增益带宽9.52MHz,相位裕度67.62°;启动时单位增益缓冲器电路的环路增益85.18dB,单位增益带宽8.93MHz,相位裕度67.2°;关断时,单位增益缓冲器电路的环路增益63.26dB,单位增益带宽2.28MHz,相位裕度88.66°.实测表明,设计降低了D类音频功放在开启和关断时的噪声.     

Improving the bandwidth gain-independence and accuracy of the current feedback amplifier

A high-performance current feedback amplifier circuit referred to as an operational current feedback amplifier is described in this paper. The technique employed involves the incorporation of the input circuit of the current feedback amplifier in the feedback loop of an operational amplifier to reduce the input impedance at the inverting terminal of the current feedback amplifier. The new circuit possesses the gain accuracy and bandwidth of the current feedback amplifier but realizes significant improvement in bandwidth accuracy and bandwidth gain-independence. Experimentally, using AD844s, an order of magnitude reduction in bandwidth variation with changing gain was achieved in the noninverting configuration and almost complete bandwidth invariance was realized in the inverting configuration.     

A 2.4-GHz sub-mW CMOS receiver front-end for wireless sensors network

A 2.4-GHz fully integrated CMOS receiver front-end using current-reused folded-cascode circuit scheme is presented. A configuration utilizing vertically stacked low-noise amplifier (LNA) and a folded-cascode mixer is proposed to improve both conversion gain and noise figure suitable for sub-mW receiver circuits. The proposed front-end achieves a conversion gain of 31.5dB and a noise figure of 11.8dB at 10MHz with 500-/spl mu/A bias current from a 1.0-V power supply. The conversion gain and noise figure improvements of the proposed front-end over a conventional merged LNA and single-balanced mixer are 11dB and 7.2dB at 10MHz, respectively, with the same power consumption of 500/spl mu/W.     

应用于DC/DC稳压器的误差放大与逻辑控制电路

设计了一种应用于DC/DC集成稳压器的误差放大与逻辑控制电路。误差放大器的核心部分采用电流镜、折叠式共源共栅等结构,显著提高了增益、电源抑制比和共模抑制比;逻辑控制部分实现了对芯片工作模式的选择控制,并具有钳位功能。采用Sanyo Hspice模型进行仿真后表明,在很宽的频带范围内,误差放大器的差模增益大于80dB;逻辑控制电路工作时序正确可靠;各项性能指标满足设计要求。     

微电容超声换能器的前端专用集成电路设计

针对微电容超声换能器(CMUT)微弱电流信号检测的要求,设计了一种用于CMUT的前端专用集成电路——运算放大器(OPA)电路。运算放大器电路采用两级放大结构,第一级采用全差分折叠-共源共栅结构,输出级采用AB类控制的轨到轨输出级,在运算放大器电路反相输入端和输出端通过一个反馈电阻实现CMUT电流信号到电压信号的转换。采用GlobalFoundries 0.18μm的标准CMOS工艺进行了仿真设计和流片,芯片尺寸为226μm×75μm。仿真结果表明,运算放大器的开环增益为62 dB,单位增益带宽为30 MHz,在3 MHz处的输入参考噪声电压为2.9μV/Hz^1/2,电路采用±3.3 V供电,静态功耗为11 mW。测试结果表明仿真与实测结果相符,该运算放大器电路能够实现CMUT微弱电流信号检测功能。     

一种适用于D类音频功放的全差分运算放大器

介绍了一种应用于超低EMI无滤波D类音频功放的全差分运算放大器结构,可构成积分器,起滤除高次谐波的作用。该运算放大器采用两级结构来获得高增益,第一级为折叠共源共栅,偏置电路采用反馈结构,给整个运算放大器提供偏置电流,从而提高电路的电源抑制比;采用伪AB类输出级提高运放的瞬态响应,稳定运放输出。仿真结果表明,该电路具有良好的性能:增益为113dB,相位裕度为67°;单位增益带宽为1.9MHz,共模抑制比为160dB,电源抑制比为82.7dB;共模反馈环路增益为120dB,相位裕度为62°。     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

一种高CMRR和PSRR的共源共栅放大器

针对传统运算放大器共模抑制比和电源抑制比低的问题,设计了一种差分输入结构的折叠式共源共栅放大器。本设计采用两级结构,第一级为差分结构的折叠式共源共栅放大器,并采用MOS管作为电阻,进一步提高增益、共模抑制比和电源电压抑制比;第二级采用以NMOS为负载的共源放大器结构,提高增益和输出摆幅。基于LITE—ON40V1．0μm工艺,采用Spectre对电路进行仿真。仿真结果表明,电路交流增益为125．8dB,相位裕度为62.8°,共模抑制比140．9dB,电源电压抑制比125．5dB。     

基于PWM的D类音频功率放大器设计

提出了基于脉冲宽度调制（PWM）的音频功率放大器,利用较新颖的反馈结构改善了总谐波失真及噪音（THD＋N）与电源抑制比（PSRR）。该电路工作电源电压2．4V-5V,电路闭环增益可以实现6dB,12dB,18dB,24dB变化。采用CSMC05CMOS工艺设计,实现了高效率,低功耗,高保真。     

Optoelectronic feedback loop for relaxation oscillation intensitynoise suppression in Tm-Ho:YAG laser

An optoelectronic feedback loop that can be used to effectively reduce the intensity noise of a 2.1 μm Tm-Ho:YAG laser has been designed. The feedback circuit is based on a variable-gain biquadratic bandpass filter with adjustable central frequency and quality factor, providing a high loop gain around the relaxation oscillation frequency of the laser and a closed-loop phase margin larger than 50°. The relaxation oscillation peak in the intensity noise spectrum was completely suppressed in closed-loop operation, and a noise reduction of up to 24 dB was obtained     

一种自适应线性化偏置的单片集成功率放大器

提出一种自适应线性化偏置的电路结构,通过调节控制电压改变偏置管的工作状态,提高功率放大电路的线性度,降低偏置电流对参考电压和环境温度的敏感度.利用双反馈环结构抑制输入阻抗随频率的变化,实现了宽带匹配,拓展了放大器的带宽.采用微波电路仿真软件AWR进行仿真,验证了带宽范围内的相位偏离度在2°以内.基于2μm InGaP/GaAs HBT工艺,设计了集成电路版图并成功流片.测试结果表明:在3.5V电压供电下,该放大器在1～2.5 GHz频带范围内,输入反射系数均在-10 dB以下,功率增益为23 dB,输出功率大于30 dBm,误差向量幅度在2.412 GHz时为.2.7％@24 dBm,最大功率附加效率达40％.     

A radio-frequency tunable active filter

A design approach for a tunable active filter of constant bandwidth and center-frequency gain is described. The approach is based on a feedback configuration with a complex zero pair in the feedback transfer function. Center frequency tuning is achieved with the variation of only one element, a potentiometer, which controls the feedback loop gain. A circuit realization using two commercial video amplifiers with RC embedding is presented. A tuning range of 25 percent at 5 MHz, with a nominal bandwidth of 90 kHz or 180 kHz, and a variation of center-frequency gain of less than /spl plusmn/1 dB over the tuning range, is obtained.     

A low-voltage low-power instrumentation amplifier based on supply current sensing technique

In this paper a new low-voltage low-power instrumentation amplifier (IA) is presented. The proposed IA is based on supply current sensing technique where Op-Amps in traditional IA based on this technique are replaced with voltage buffers (VBs). This modification results in a very simplified circuit, robust performance against mismatches and high frequency performance. To reduce the required supply voltage, a low-voltage resistor-based current mirror is used to transfer the input current to the load. The input and output signals are of voltage kind and the proposed IA shows ideal infinite input impedance and a very low output one. PSPICE simulation results, using 0.18 μm TSMC CMOS technology and supply voltage of ±0.9 V, show a 71 dB CMRR and a 85 MHz constant −3 dB bandwidth for differential-mode gain (ranging from 0 dB to 18 dB). The output impedance of the proposed circuit is 1.7 Ω and its power consumption is 770 µW. The method introduced in this paper can also be applied to traditional circuits based on Op-Amp supply current sensing technique.     

应用于5GHz频段带ESD保护的可变增益低噪声放大器

本文给出了应用于5GHz频段的可变增益低噪声放大器。详细分析了输入寄生电容对源极电感负反馈低噪声放大器的影响,给出了一种新的ESD和LNA联合设计的方法,另外,通过在第二级中加入一个简单的反馈回路实现了增益的可变。测试结果表明： 可变增益低噪声放大器增益变化范围达25dB (-3.3dB～21.7dB),最大增益时噪声系数为2.8dB,最小增益时三阶截点为1dBm,在1.8V电源电压下功耗为9.9mW。     

2.8～4.2GHz MMIC低噪声放大器

报道了基于0.25μm GaAs PHEMT工艺的2.8～4.2GHz MMIC低噪声放大器,详细介绍和分析了低噪声放大器的器件基础和设计原理,设计采用源极串联电感负反馈方法使输入阻抗共轭匹配和最小噪声匹配趋于一致,偏置网络采用自偏置栅压、单电源供电,并用ADS软件仿真。电路评估板选用Rogers RO4350B,在2.8～4.2GHz频段内测得增益大于20dB、增益平坦度小于2.5dB、噪声系数小于2.3dB、输入输出驻波比小于2.0。     

一种采用有源电感的可调增益小面积超宽带低噪声放大器

设计了一款采用可调谐有源电感（TAI）的可调增益的小面积超宽带低噪声放大器(LNA),输入级采用共基极结构,输出级采用射随器结构,分别实现了宽带输入和输出匹配;放大级采用带有反馈电阻的共射共基结构以取得宽的带宽,并采用TAI作负载,通过调节TAI的多个外部偏压使LNA的增益可调。结果表明,该LNA在2~9GHz的频带内,通过组合调节有源电感调节端口的偏压可实现S21在16.5~21.1dB的连续可调;S11小于-14.7dB;S22小于-19.3dB;NF小于4.9dB;芯片面积仅为0.049mm2。