RF circuit design aspects of spiral inductors on silicon

The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q an the performance of radio-frequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5-100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q     

On the design of RF spiral inductors on silicon

This review of design principles for implementation of a spiral inductor in a silicon integrated circuit fabrication process summarizes prior art in this field. In addition, a fast and physics-based inductor model is exploited to put the results contributed by many different groups in various technologies and achieved over the past eight years into perspective. Inductors are compared not only by their maximum quality factors (Q/sub max/), but also by taking the frequency at Q/sub max/, the inductance value (L), the self-resonance frequency (f/sub SR/), and the coil area into account. It is further explained that the spiral coil structure on a lossy silicon substrate can operate in three different modes, depending at first order on the silicon doping concentration. Ranging from high to low substrate resistivity, inductor-mode, resonator-mode, and eddy-current regimes are defined by characteristic changes of Q/sub max/, L, and f/sub SR/. The advantages and disadvantages of patterned or blanket resistive ground shields between the inductor coil and substrate and the effect of a substrate contact on the inductor are also addressed in this paper. Exploring optimum inductor designs under various constraints leverages the speed of the model. Finally, in view of the continuously increasing operating frequencies in advancing to new generations of RF systems, the range of feasible inductance values for given quality factors are predicted on the basis of optimum technological features.     

CMOS-compatible surface-micromachined suspended-spiral inductors for multi-GHz silicon RF ICs

Fully CMOS-compatible, highly suspended spiral inductors have been designed and fabricated on standard silicon substrates (1/spl sim/30 /spl Omega//spl middot/cm in resistivity) by surface micromachining technology (no substrate etch involved). The RF characteristics of the fabricated inductors have been measured and their equivalent circuit parameters have been extracted using a conventional lumped-element model. We have achieved a high peak Q-factor of 70 at 6 GHz with inductance of 1.38 nH (at 1 GHz) and a self-resonant frequency of over 20 GHz. To the best of our knowledge, this is the highest Q-factor ever reported on standard silicon substrates. This work has demonstrated that the proposed microelectromechanical systems (MEMS) inductors can be a viable technology option to meet the today's strong demands on high-Q on-chip inductors for multi-GHz silicon RF ICs.     

On-chip spiral inductors with patterned ground shields for Si-basedRF ICs

This paper presents a patterned ground shield inserted between an on-chip spiral inductor and silicon substrate. The patterned ground shield can be realized in standard silicon technologies without additional processing steps. The impacts of shield resistance and pattern on inductance, parasitic resistances and capacitances, and quality factor are studied extensively. Experimental results show that a polysilicon patterned ground shield achieves the most improvement. At 1-2 GHz, the addition of the shield increases the inductor quality factor up to 33% and reduces the substrate coupling between two adjacent inductors by as much as 25 dB. We also demonstrate that the quality factor of a 2-GHz LC tank can be nearly doubled with a shielded inductor     

Experimental analysis of the effect of metal thickness on the quality factor in integrated spiral inductors for RF ICs

The effect of metal thickness on the quality (Q-) factor of the integrated spiral inductor is investigated in this paper. The inductors with metal thicknesses of 5/spl sim/22.5 /spl mu/m were fabricated on the standard silicon substrate of 1/spl sim/30 /spl Omega//spl middot/cm in resistivity by using thick-metal surface micromachining technology. The fabricated inductors were measured at GHz ranges to extract their major parameters (Q-factor, inductance, and resistance). From the experimental analysis assisted by FEM simulation, we first reported that the metal thickness' effect on the Q-factor strongly depends on the innermost turn diameter of the spiral inductor, so that it is possible to improve Q-factors further by increasing the metal thickness beyond 10 /spl mu/m.     

Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-/spl mu/m RFCMOS technology, experimental results in this paper reveal that inductors' core diameters must be adequately large, more than 100 /spl mu/m, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit's operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.     

Thermal effects in suspended RF spiral inductors

Self-heating effects on integrated suspended and bulk spiral inductors are explored. A dc current is fed through the inductors during measurement to emulate dc and radio frequency power loss on the inductor. A considerable drop in Q by /spl sim/18% at 36.5 mW is observed for suspended coils with 3-/spl mu/m aluminum metallization compared to reference inductors on bulk-Si. Simulations in Ansoft's ePhysics indicate that, due to the thermal isolation of the suspended coil, the power loss from resistive self-heating in the metal has to be transferred outwards through the metal turns. This also results in a thermal time constant. This time constant is measured to be /spl sim/10 ms, meaning that it can affect power circuits operating in pulsed mode.     

Characterization and modeling of on-chip spiral inductors for Si RFICs

The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.     

Scalable compact circuit model and synthesis for RF CMOS spiral inductors

A scalable industry-oriented, 24-element "2-/spl pi/" compact circuit model for on-chip RF CMOS spiral inductors is presented. It has a good accuracy up to self-resonant frequency (SRF). Two levels of modeling approaches are provided, which are: 1) the fixed model, which extracts the values of circuit elements directly from the measured S-parameters of a given device, achieving high accuracy, but no scalability and 2) the scalable model, in which circuit elements are related to the geometry (i.e., layout) through a set of formulas with model parameters calibrated upon a few testing devices. The synthesis procedure is also discussed, which includes the scalable model and a SPICE simulator as the evaluation method within the iteration loop.     

Design optimization of switchable multi-port spiral inductors

In this paper, we develop a design optimization methodology for switchable multi-port spiral inductors in fully integrated wireless systems. The methodology simultaneously maximizes the inductor’s performance for multiple inductance values and operating frequencies. We utilize multi-level optimization techniques to efficiently design the geometry of the switchable inductor structure. The methodology can produce designs with significantly larger quality factors than those obtained by optimizing the inductor design for a single inductance value and operating frequency.     

Fabrication and performance of novel RF spiral inductors on silicon

This paper presents and discusses the fabrication and the performance of RF circular spiral inductors on silicon. The substrate materials underneath the inductor coil are removed by wet etching process. In the fabrication process, fine polishing of the photoresist is used to simplify the processes and ensure the seed layer and the pillars contact perfectly, and dry etching technique is used to remove the seed layer. The results show that Q-factor of the novel inductor is greatly improved by removing the silicon underneath the inductor coil. The spiral inductor for line width of 50 μm has a peak Q-factor of 17 at frequency of 1 GHz. The inductance is about 3.2 nH in the frequency range of 0.05-3 GHz and the resonance frequency of the inductors is about 6 GHz. If the strip is widened to 80 μm, the peak Q-factor of the inductor reduces to about 10 and the inductance is 1.5 nH in the same frequency range.     

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.     

Nonlinear characteristics of on-chip spiral inductors under high RF power

This paper explores silicon CMOS on-chip spiral inductors performance degradation under high RF power. A novel methodology to calibrate and characterize on-chip spiral inductor with large signal inputs (high/medium power) is presented. Experiments showed 12% degradation of quality factor in a particular inductor design when 34 dBm RF power was applied. The degradation of quality factor of inductor can be attributed to a local self heating effect. Thermal imaging of such an inductor under high RF power validates the hypothesis.     

Comprehensive study on low-frequency noise characteristics insurface channel SOI CMOSFETs and device design optimization for RF ICs

Low-frequency (LF) noise, a key figure-of-merit to evaluate device technology for RF systems on a chip, is a significant obstacle for CMOS technology, especially for partially depleted (PD) silicon-on-insulator (SOI) CMOS due to the well-known kink-induced noise overshoot. While the dc kink effect can be suppressed by either using body contact technologies or shifting toward fully depleted (FD) operation, the noise overshoot phenomena still resides at high frequency for either FD SOI or poor body-tied (BT) SOI CMOSFETs. In this paper, floating body-induced excess noise in SOI CMOS technology is addressed, including the impact from floating body effect, pre-dc kink operation, and gate overdrive, followed by the proposal of a universal LF excess noise model. As the physical mechanism behind excess noise is identified, this paper concludes with the suggestion of a device design methodology to optimize LF noise in SOI CMOSFET technology     

Analysis and synthesis of on-chip spiral inductors

This paper presents a physically based compact model for estimating high-frequency performance of spiral inductors. The model accurately accounts for skin and proximity effects in the metal conductors as well as eddy current losses in the substrate. The model shows excellent agreement with measured data mostly within 10% across a variety of inductor geometries and substrate dopings up to 20 GHz. A web-based spiral inductor synthesis and analysis tool COILS, which makes use of the compact models, is presented. An optimization algorithm using binary searches speeds up the synthesis of inductor designs.     

Efficient modeling of RF CMOS spiral inductors using generalized knowledge-based neural network

Efficient modeling of RF CMOS spiral inductors by virtue of a novel generalized knowledge-based neural network (GKBNN) is presented. Prior knowledge of on-chip inductors is used for constructing the GKBNN. This new modeling approach also exploits merits of the iterative multi stage algorithm. This GKBNN has much enhanced learning and generalization capabilities. Comparing with the conventional neural network or the knowledge-based neural network, this new GKBNN model can map the input–output relationships with fewer hidden neurons and has higher reliability for generalization. As a consequence, this GKBNN model can run as fast as an approximate equivalent circuit model yet generate results as accurate as detailed electromagnetic simulations. Experiments are included to demonstrate merits and efficiency of this new approach.     

Improvement of the quality factor of RF integrated inductors bylayout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency     

RF packaging and passives: design, fabrication, measurement, and validation of package embedded inductors

Design, modeling, and characterization of inductors embedded in a package substrate promising higher quality factor (Q) and lower cost than on-chip inductors is described. In addition to the problem of large conductor losses, on-die inductors with or without magnetic materials consume considerable die area and require the removal of the first-level interconnect bumps beneath them to maintain a reasonably high Q value. Moving inductors to the package eliminates the need for bump array depopulation and, thus, mitigates the potential reliability problems caused by voids in the epoxy underfill between the die and the substrate. Competency developed to design, fabricate, and characterize inductors based on standard organic flip-chip packaging technology is described. Physical design details along with measurement procedures and results are discussed. In addition, modeling techniques for achieving good correlation to measured data are included.     

Improved and physics-based model for symmetrical spiral inductors

Recent growth in RF applications has increased the use of spiral inductors and thus demanded a more accurate model for such devices. In this paper, the authors focus on the model development of spiral inductors with symmetrical terminals, but the same approach can be applied readily to asymmetrical inductors. Relevant and important physics such as the current crowding in metal line, frequency-dependent permittivity in oxide, and overlap parasitics are accounted for. Experimental data and results calculated from the existing inductor models are included in support of the model development.     

Parasitic-aware RF circuit design and optimization

RF circuit synthesis techniques based on particle swarm optimization and adaptive simulated annealing with tunneling are described, and comparisons of parasitic-aware designs of an RF distributed amplifier and a nonlinear power amplifier are presented. Synthesized in 0.35-/spl mu/m digital CMOS using a single 3.3-V power supply, the designs provide an 8-dB gain and 8-GHz bandwidth for a four-stage distributed amplifier, and 1.2-W output power with 55% drain efficiency at 900 MHz for a three-stage power amplifier. A standard circuit simulator, HSPICE or SPECTRE, embedded in an optimization loop is used to evaluate cost functions. The proposed design and optimization methodology is computationally efficient and robust in searching complex multidimensional design spaces.