1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.     

High-speed monolithically integrated silicon photoreceivers fabricated in 130-nm CMOS technology

A complementary metal-oxide-semiconductor (CMOS) monolithically integrated photoreceiver is presented. The circuit was fabricated in a 130-nm unmodified CMOS process flow on 2-/spl mu/m-thick silicon-on-insulator substrates. The receiver operated at 8 Gb/s with 2-dBm average input optical power and a bit error rate of less than 10/sup -9/. The integrated lateral p-i-n photodetector was simultaneously realized with the amplifier and had a responsivity of 0.07 A/W at 850 nm. The measured receiver sensitivities at 5, 3.125, 2, and 1 Gb/s, were -10.9, -15.4, -16.5, and -19 dBm, respectively. A 3-V single-supply operation was possible at bit rates up to 3.125 Gb/s. The transimpedance gain of the receivers was in the range 53.4-31 dB/spl Omega/. The circuit dissipated total power between 10 mW and 35 mW, depending on the design.     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

Bandwidth enhancement for transimpedance amplifiers

A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known low-pass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18-/spl mu/m BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dB/spl Omega/, while drawing 55 mA from a 2.5-V supply. The input sensitivity of the TIA is -18 dBm for a bit error rate of 10/sup -12/.     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit

A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery (CDR) circuit using the full-rate bang-bang phase detector is presented. A frequency detector is proposed to eliminate the harmonic locking problem even with a wide range of data rates and its theoretical analysis is also discussed. A quadrature divider is also presented to generate the clocks with accurate quadrature phases. This CDR circuit has been realized in a 0.18-/spl mu/m CMOS process and its die area is 1.1/spl times/0.8 mm/sup 2/. It consumes 95 mW at the highest bit rate of 3.125 Gbps. It can recover the NRZ data of a 2/sup 31/-1 PRBS with the bit rate ranging from 155.52 Mbps to 3.125Gbps for the incremental frequency acquisition and the NRZ data of a 2/sup 7/-1 PRBS for the decremental frequency acquisition. All the measured bit error rates are less than 10/sup -12/.     

A thyristor-based photoreceiver based on the dual-channel double-heterostructure optoelectronic switch

A new approach to photoreceiver design is described based on the functionality of an optoelectronic thyristor. The receiver eliminates the transimpedance amplifier and the decision circuit by utilizing the internal gain of the thyristor and its nonlinear thresholding property. The sensitivity is determined by the shot noise on the input signal to be 360 photons per bit at a bit-error rate of 10/sup -9/. The speed of the photoreceiver is determined by the switching times of the thyristor. An output voltage signal from 0 to 1.5 V is obtained with switch on and off times of 12.5 ps and input photocurrent densities of 10/sup 4/ A/cm/sup 2/. The switch off time is equally as fast as the switch on due to the absence of stored charge in the modulation doped structure. The key to the high speed is the utilization of the third and fourth terminal contacts to the thyristor and the integration of the biasing transistors, which control the switching currents. An input optical signal of 0.5 mW will achieve this bandwidth in a device size of 0.2 /spl mu/m/spl times/12.5 /spl mu/m.     

10-gb/s operation of an In/sub 0.53/Ga/sub 0.47/As p-i-n photodiode on metamorphic InGaP buffered semi-insulating GaAs substrate

The SONET OC-192 receiving performance of In/sub 0.53/Ga/sub 0.47/As p-i-n photodiode grown on linearly graded metamorphic In/sub x/Ga/sub 1-x/P buffered GaAs substrate is reported. With a low-cost TO-46 package, such a device exhibits a frequency bandwidth up to 8 GHz, a bit-error rate (BER) of 10/sup -9/ at 10 Gb/s, a sensitivity of -17.8 dBm, and a noise equivalent power of 3.4/spl times/10/sup -15/ W/Hz/sup 1/2/ owing to its ultralow dark current of 3.6/spl times/10/sup -7/ A/cm/sup 2/. Eye diagram analysis at 10 Gb/s without transimpedance amplification reveals a statistically distributed Q-factor of 8.21, corresponding to a minimum BER of 1.1/spl times/10/sup -16/ at receiving power of -6 dBm.     

An inductance enhancement technique and its application to a shunt-peaked 2.5 Gb/s transimpedance amplifier design

This brief presents a bandwidth enhancement technique that is applicable to gigahertz-range broadband circuits. Using the inductance enhancement technique proposed in this brief, a 2.5-Gb/s transimpedance amplifier (TIA) has been implemented based on a 0.35-/spl mu/m CMOS technology. With the input noise reduction, the TIA with the proposed active inductor loads improves the overall system performances including more that 90% increase in bandwidth. Measurements show the bandwidth of 1.73 GHz, transimpedance gain of 68 dB/spl Omega/, and the averaged input referred noise current of 3.3 pA//spl radic/Hz, respectively, while dissipating 50 mW of dc power.     

A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

This paper describes the design of a transimpedance amplifier (TIA) for a low-power, short-distance, high-density fiber-optic interconnect communication system. The single-ended circuit has been designed in an 80-nm digital CMOS process and consumes only 2.2 mW from a 1-V supply. The measured results show a transimpedance gain of 52 dB/spl Omega/ and a large bandwidth of 20 GHz. This work presents the highest bandwidth at the lowest power consumption for CMOS transimpedance amplifiers reported to date.     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

Three-stage burst-mode transimpedance amplifier in deep-sub-/spl mu/m CMOS technology

A transimpedance amplifier, designed in a digital 120-nm CMOS technology, used as preamplifier for optical burst-mode receivers in passive optical networks is presented. A wide optical input power range of 27 dB can be handled with a variable transimpedance without stability problems by varying the open-loop gain by a factor of 115. Noise and stability analysis of the optical receiver are presented. Sensitivities of - 31.3 dBm at 622 Mb/s and - 28.6 dBm at 1.25 Gb/s with a bit error ratio of 10/sup -10/ and a pseudorandom bit stream of 2/sup 31/-1 are achieved with a power consumption of 88.5 mW.     

A 2.5-mW SOS CMOS optical receiver for chip-to-chip interconnect

This paper reports on the design of a differential optical receiver in silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS). The low-power characteristics (2.5 mW) and small footprint make it a good candidate for two-dimensional optoelectronic interchip interconnects where the transparency of the substrate facilitates system integration and packaging. A differential transimpedance amplifier (TIA) with positive feedback at the front end extends the bandwidth of traditional differential TIAs when the capacitance of the photodetector is smaller than the capacitance of the gates in the differential pair. The full receiver tested in the 0.5-/spl mu/m ultrathin silicon (UTSi) SOS-CMOS Peregrine process consumes 2.5 mW when operated at or near gigabit rates, with bit-error rates of better than 10/sup -12/ taken at 750 Mb/s.     

1-Gb/s 80-dB/spl Omega/ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-/spl mu/m standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dB/spl Omega/ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-/spl mu/A average input noise current, -17-dBm sensitivity for 10/sup -12/ bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.     

Flash ADC architecture

A 4-bit, 2.5 V modified flash analogue-to-digital converter (ADC) has been designed. In this design, the new flash topology only requires 2/sup (N-2)/+2 comparators. For comparison reasons, this new ADC architecture is operated at 400 MHz, consumes a total power of 1.68 mW and generates a total noise power of 4.86/spl times/10/sup -15/. /spl Delta/f(V/sup 2/) at this frequency.     

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

This paper describes the design and implementation of a quad high-speed transceiver cell fabricated in 0.13-/spl mu/m CMOS technology. The clocking circuit of the cell employs a dual-loop architecture with a high-bandwidth core phase-locked loop (PLL) and low-bandwidth digitally controlled interpolators. To achieve low jitter while maintaining low power consumption, the dual-loop PLL uses two on-chip linear regulators of different bandwidths, one for the core and the other for the interpolator loop. The prototype chip operates from 400 Mb/s to 4 Gb/s with a bit error rate of <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400-mV output swing driving double terminated links.     

Demonstration of 1789 V, 6.68 m/spl Omega/ /spl middot/ cm/sup 2/ 4H-SiC merged-PiN-Schottky diodes

The design, fabrication and characterisation of a high performance 4H-SiC diode of 1789 V-6.6 A with a low differential specific-on resistance (R/sub SP/spl I.bar/ON/) of 6.68 m/spl Omega/ /spl middot/ cm/sup 2/, based on a 10.3 /spl mu/m 4H-SiC blocking layer doped to 6.6/spl times/10/sup 15/ cm/sup -3/, is reported. The corresponding figure-of-merit of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ for this diode is 479 MW/cm/sup 2/, which substantially surpasses previous records for all other MPS diodes.     

A 40-Gb/s Transimpedance Amplifier in 0.18-$mu$m CMOS Technology

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/P_de) of 180.1 GHzOmega/mW.     

Wideband quantum-dash-in-well superluminescent diode at 1.6 /spl mu/m

We demonstrate broadband superluminescent diode at /spl sim/1.6-/spl mu/m peak emission wavelength using InAs-InAlGaAs quantum-dash-in-well structure on InP substrate. The fabricated device exhibits the close-to-Gaussian emission with a bandwidth of up to 140 nm. The device produces a low spectrum ripple of 0.3dB and an integrated power of 1.7 mW with the corresponding bandwith of 110 nm measured at 20 /spl deg/C under 8 kA/cm/sup 2/.