视频编码系统模拟软件包的设计研究

视频编码国际标准的算法具有安全的开放性，因此，软件模拟是视频编码系统设计中十分重要的环节，本文采用面向对象技术，利用速成原型建模，设计了可模拟多个视频编码标准的软件包，该模拟软件包满足编码系统中扩充性的要求，适于研究不同压压缩算法，并模拟视频编码系统的执行，为构造实时编码系统提供正确的设计数据和适用的算法。     

Overview of the MPEG Reconfigurable Video Coding Framework

Video coding technology in the last 20 years has evolved producing a variety of different and complex algorithms and coding standards. So far the specification of such standards, and of the algorithms that build them, has been done case by case providing monolithic textual and reference software specifications in different forms and programming languages. However, very little attention has been given to provide a specification formalism that explicitly presents common components between standards, and the incremental modifications of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO standard currently under its final stage of standardization, aiming at providing video codec specifications at the level of library components instead of monolithic algorithms. The new concept is to be able to specify a decoder of an existing standard or a completely new configuration that may better satisfy application-specific constraints by selecting standard components from a library of standard coding algorithms. The possibility of dynamic configuration and reconfiguration of codecs also requires new methodologies and new tools for describing the new bitstream syntaxes and the parsers of such new codecs. The RVC framework is based on the usage of a new actor/ dataflow oriented language called CAL for the specification of the standard library and instantiation of the RVC decoder model. This language has been specifically designed for modeling complex signal processing systems. CAL dataflow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. The paper gives an overview of the concepts and technologies building the standard RVC framework and the non standard tools supporting the RVC model from the instantiation and simulation of the CAL model to software and/or hardware code synthesis.     

基于Galois域Reed-Solomon码的数据包层FEC编码软件实现

本文提出一种基于Galois域Reed-Solomon码的数据包层FEC编码软件实现方法。文中利用Galois域的运算封闭性和Reed-Solomon码的变换特笥解决了FEC编码等字长变换问题；通过查找表实现多项式运算，有效降低多项式运算的复杂度，提高了软件FEC编码的效率；文中还介绍了查找表的生成方法。实验表明，基于本文所提出的方法，能够用软件实现高效的数据包层FEC编/解码。     

Generation of uniform amplitude complex code sets with lowcorrelation sidelobes

The performances of generated test code sets are compared to other phase coding and theoretical limits. The results presented show that the generation algorithm produces uniform amplitude complex code sets with low autocorrelation sidelobes and low cross-correlation outputs. The mainlobe to peak sidelobe ratio (MPSR) gains over binary codes could lead to significant performance improvements in both communication and radar systems that require multiple codes. The Doppler characteristics of the generated codes are comparable to those of binary phase codes. Although the generation times are long, they are not impractical given current and projected processing technology     

光存储中RS纠错码两种实现算法的研究

以光存储应用为背景,针对盘片记录信息固有的高原生误码率问题,从目前CD,DVD的纠错编码方案出发,设计并实现一种合适的差错控制方法来保证数据读写的正确性。分析了实现Reed Solomon(RS)纠错编码的Berlekamp Massey(BM)算法和Peterson Gorentstein-Zierler(PGZ)算法的原理和各自的实现途径,比较了这两种算法的优缺点,得出了它们的不同应用条件。采用高速硬件描述语言(VHDL)成功实现了PGZ算法,并得到了理想的仿真结果。     

Decoding the Golay code with Venn diagrams

A decoding algorithm, based on Venn diagrams, for decoding the [23, 12, 7] Golay code is presented. The decoding algorithm is based on the design properties of the parity sets of the code. As for other decoding algorithms for the Golay code, decoding can be easily done by hand     

基于XML的代码自动生成工具

代码自动生成作为一种程序自动化技术,可有效解决现代大规模软件开发过程中遇到的重复编写代码问题,提高了软件开发的效率和质量。文中介绍了一种基于XML的代码生成技术,并以XML转换技术为基础,给出了XML的代码生成工具的结构设计,及其实现框架和关键步骤。以该工具在雷达建模仿真过程中的应用实例,验证了基于XML的代码生成工具可减少重复代码编写,降低因手工编写带来的编码错误,从而提高了代码的编写质量及效率,使大规模软件开发和维护更简便。     

Design of computer controlled combustion engines

Globalization and growing new markets, as well as increasing emission and fuel consumption requirements, force the car manufacturers and their suppliers to develop new engine control strategies in shorter time periods. This can mainly be reached by development tools and an integrated hardware and software environment enabling rapid implementation and testing of advanced engine control algorithms.

The structure of a rapid control prototyping (RCP) system is explained, which allows fast measurement signal evaluation, and rapid prototyping of advanced engine control algorithms. A hardware-in-the-loop simulator for diesel engine control design is illustrated, simulation results for a 40 tons truck are presented. Providing efficient engine models for the proposed development tools, a dynamic local linear neural network approach is explained and applied for modelling the NO_x emission characteristics of a 1.9 l direct injection diesel engine. Furthermore the application of a RCP system is exemplified by the application of combustion pressure based closed-loop ignition timing control for a SI engine. Experimental results are shown for a 1.0 l SI engine on a dynamic engine test stand.     

Matlab平台DSP自动代码生成技术研究

Oral-DSP编程难度大,耗时长的问题,给出了一种综合运用Matlab软件、CodeComposerStudio（CCS）软件及其内嵌工具和连接软件进行自动代码生成的方法。重点研究DM642EVM板的自动代码生成方法,并以边缘检测实验为例,验证自动生成代码的可执行性。实验结果表明,该代码生成方法不仅具有极高的生成效率,而且灵活易用;生成的可执行代码可以在DSP板上顺利运行,并可取得非常好的处理结果。     

Decoding of the Golay code

A decoding algorithm based on revised syndromes to decode the binary (23, 12, 7) Golay code is presented. The algorithm strongly depends on the algebraic properties of the code. For the algorithm, the worst complexity is ~576 mod 2 additions, which is less than that of the algorithms available for the code; the average complexity is approximately 224 mod 2 additions, which is also less than that of the known algorithms for the code     

一种混合多边缘型LDPC码密度进化算法

在二进制输入加性高斯白噪声信道下，研究了基于多边缘型低密度奇偶校验码（Multi-edge Low Density Parity Check，MET-LDPC）的密度进化算法。针对高斯近似算法在前期迭代中的不准确问题，提出了一种改进算法。在分析MET-LDPC码的密度进化的基础上，将全密度进化与高斯近似算法结合，通过设置切换限制条件，弥补早期迭代的不准确，提高编码阈值估计的准确性。仿真结果表明,与MET-LDPC全密度进化算法相比，所提算法可以有效提高编码阈值估计的准确性，对LDPC编码的设计有一定的参考价值。     

A difference-set cyclic code (1057,813,34)

This paper presents an overview of the implementation of a difference-set cyclic code (1057,813,34). It is easy to achieve coding and decoding circuits. The decoding lays on the analysis of the composite remainder R_c (x) and the use of a decoding matrix of 33 Boolean equations. The error-correcting algorithm has been improved, so the difference-set cyclic code (1057,813,34) can correct up to 26 random errors instead of the 16 previous random errors found by the theory. Moreover, 3 decoding algorithms have been simulated and allow the comparison of their respective efficiency. The hardware achievement is quite easy because the necessary logical elements such as shift delay registers, positive-and gates, positive-or gates, positive-exclusive-or gates exist as a set of libraries.     

Coded QAM using a binary convolutional code

As an alternative to trellis coding, a binary convolutional code is considered for use with such nonbinary modulation schemes as quadrature amplitude modulation (QAM). A Gray code is used to map the encoder output to the M-ary QAM constellation. The focus is on the design of 16-ary coded QAM with a rate 3/4 punctured convolutional code of a constraint length 7. A quantized binary metric generation method is proposed and shown to be suboptimum as compared to the direct use of a M-ary unquantized metric. Impressive coding gains and bandwidth efficiency are shown in comparison with uncoded systems     

Rapid prototyping of radar algorithms [Applications Corner]

Rapid prototyping of advanced signal processing algorithms is critical to developing new radars. Signal processing engineers usually use high level languages like MATLAB, IDL, or Python to develop advanced algorithms and to determine the optimal parameters for these algorithms. Many of these algorithms have very long execution times due to computational complexity and/or very large data sets, which hinders an efficient engineering development workflow. That is, signal processing engineers must wait hours, or even days, to get the results of the current algorithm, parameters, and data set before making changes and refinements for the next iteration. In the meantime, the engineer may have thought of several more permutations that he or she wants to test.     

Embedded image coding using zerotrees of wavelet coefficients

The embedded zerotree wavelet algorithm (EZW) is a simple, yet remarkably effective, image compression algorithm, having the property that the bits in the bit stream are generated in order of importance, yielding a fully embedded code. The embedded code represents a sequence of binary decisions that distinguish an image from the “null” image. Using an embedded coding algorithm, an encoder can terminate the encoding at any point thereby allowing a target rate or target distortion metric to be met exactly. Also, given a bit stream, the decoder can cease decoding at any point in the bit stream and still produce exactly the same image that would have been encoded at the bit rate corresponding to the truncated bit stream. In addition to producing a fully embedded bit stream, the EZW consistently produces compression results that are competitive with virtually all known compression algorithms on standard test images. Yet this performance is achieved with a technique that requires absolutely no training, no pre-stored tables or codebooks, and requires no prior knowledge of the image source. The EZW algorithm is based on four key concepts: (1) a discrete wavelet transform or hierarchical subband decomposition, (2) prediction of the absence of significant information across scales by exploiting the self-similarity inherent in images, (3) entropy-coded successive-approximation quantization, and (4) universal lossless data compression which is achieved via adaptive arithmetic coding     

The REAR Framework for Emulation and Analysis of Embedded Hard Real-Time Systems

The aim of rapid prototyping real-time applications is to substantially reduce development times by confirming the functional and temporal requirements of the application at a very early stage of development with the help of an executable prototype. Hence, the real-time rapid prototyping system presented in this paper integrates two complementary tasks: On one hand it provides an automated design environment for a rapid and facile generation of a working prototype. On the other hand, the design process is extended with real-time requirement specification and analysis in order to prove that the embedded system will meet all timing requirements, and to verify that the timing requirements have been modeled correctly. The REAR framework uses annotated SDL for the system specification, from which both, the compilable source codes and the real-time analysis model are generated. After instrumentation for timing measurements, the C and VHDL source code is compiled and synthesized, linked with communication libraries and executed on the configurable, heterogeneous multiprocessor target system. Several case studies demonstrate the feasibility of this approach.     

VLSI implementation of a maximum-likelihood decoder for the Golay(24, 12) code

J.H. Conway and N.J.A. Sloane (1986) have introduced an algorithm for the exact maximum-likelihood decoding of the Golay (24, 12) code in the additive white Gaussian noise channel that requires significantly fewer computations than previous algorithms. An efficient bit-serial VLSI implementation of this algorithm is described. The design consists of two chips developed using path-programmable logic (PPL) and an associated system of automated design tools for three-μm NMOS technology. It is estimated that this decoder will produce an information bit every 1.6-2.4 μs. Higher speeds can be achieved by using a faster technology or by replicating the chips to perform more operations in parallel     

低重分配概率的OVSF码重分配算法

在采用正交可变长扩频因子(OVSF)码作为信道化码的直接序列扩频码分多址系统中,提出用重分配概率作为重分配算法的一个新的评价指标,重分配概率越小,系统的计算复杂度越低。进而提出一种低重分配概率的、基于空码容量的重分配算法,在解决本次码阻塞的同时,兼顾对未来高数据速率的呼叫的支持能力,减少未来码阻塞发生。仿真证实,重分配概率比已有2种重分配算法都小。     

How rapid is rapid prototyping?

New methodologies, engineering processes and support environments are beginning to emerge for embedded signal-processing systems. The main objectives are to enable industry to field state-of-the-art products in less time and with lower costs, including retrofits and upgrades, based predominantly on commercial off-the-shelf (COTS) components and the model-year concept. One of the cornerstones of the new methodologies is the concept of rapid prototyping. This is the ability to rapidly and seamlessly move from functional design, to architectural design, to implementation, through automatic code generation tools, onto real-time COTS test beds. This paper tries to quantify the term 'rapid' and provides results-metrics-from two independent benchmarks: a radar and sonar beamforming application subset. The metrics show that the rapid prototyping process may be 16 times faster than a conventional process