Analysis of partially shared buffering for WDM optical packetswitching

A new WDM packet switch architecture, partially shared buffering, is proposed. This architecture, in addition to dedicating an individual prime buffer for each output, incorporates a separate buffer for all the outputs to share. Based on this architecture, a lower packet loss probability can be achieved without the need of either dramatically increasing the size of each prime output buffer or deploying a large number of wavelength converters. The performance of the new architecture has been extensively studied by means of numerical simulations     

Odd-even input-buffered multicast switch

An input buffered packet switch called the odd-even multicast switch is proposed. The packet splitting probability of the proposed switch is derived and the packet output contention is resolved using the cyclic-priority reservation (CPR) algorithm. The throughput and mean packet delay of the proposed switch are compared with a simple input buffered switch. It is found that the proposed switch gives a significant performance improvement at the expense of extra packet splitting overhead     

A buffer management scheme for the SCOQ switch under nonuniformtraffic loading

The SCOQ switch is a Batcher-banyan based high performance fast packet switch with shared concentration and output queueing, with a maximum of L(相似文献   

Variable IP packets buffer management schemes for optical packet switching

Effective buffering of optical packets is essential to the efficient working of optical packet switches. In this paper three new schemes, which involve sorting and finding the least occupied buffer, are proposed. Their performance is compared with the common round-robin scheme. The results show that all these new schemes are able to enhance the optical packet switch performance significantly in terms of packet drop/loss probability. In addition, the results show that not all the newly arrived packets need to be sorted in order to obtain the minimum packet drop probability. As computation/processing time is significant in optical packet switching, partial sorting of the newly arrived packets with tolerable packet drop probability appears to be a viable proposition. Conversely, a complete sort of newly arrived packets wastes packet processing time unnecessarily while significantly increasing the packet drop probability.     

Performance of two-stage shared fiber delay line optical packet switch under bursty traffic

Packet contention is a major issue in an optical packet switching network. It is not a trivial task to resolve contention due to lack of optical RAM technology. This article proposes a two-stage shared fiber delay line (FDL) optical packet switch for contention resolution. In this article, shared FDLs are used to buffer optical packets, in which a pool of buffer memory is shared among all switch output ports. Most of the existing optical buffering schemes are output-based which require a huge number of FDLs as well as a larger switch size that incur extra implementation cost. However, a shared buffering approach is considered in this article in order to reduce implementation cost. In this article, FDLs are implemented in two stages using an extremely simple auxiliary switch. The proposed switch architecture leads to more efficient use of buffer space. The superiority of the proposed switch architecture has been established by means of extensive simulations. The performance of the proposed switch is investigated under bursty traffic. Simulation result shows that the proposed switch can achieve satisfactory performance at the price of a reasonable amount of FDLs. Moreover, the significance of the proposed switch is confirmed by simulation.     

Queueing in high-performance packet switching

The authors study the performance of four different approaches for providing the queuing necessary to smooth fluctuations in packet arrivals to a high-performance packet switch. They are (1) input queuing, where a separate buffer is provided at each input to the switch; (2) input smoothing, where a frame of b packets is stored at each of the input line to the switch and simultaneously launched into a switch fabric of size Nb×Nb; (3) output queuing, where packets are queued in a separate first-in first-out (FIFO) buffer located at each output of the switch; and (4) completely shared buffering, where all queuing is done at the outputs and all buffers are completely shared among all the output lines. Input queues saturate at an offered load that depends on the service policy and the number of inputs N, but is approximately 0.586 with FIFO buffers when N is large. Output queuing and completely shared buffering both achieve the optimal throughput-delay performance for any packet switch. However, compared to output queuing, completely shared buffering requires less buffer memory at the expense of an increase in switch fabric size     

The bypass queue in fast packet switching

The telecommunications networks of the future are likely to be packet switched networks consisting of wide bandwidth optical fiber transmission media, and large, highly parallel, self-routing switches. Recent considerations of switch architectures have focused on internally nonblocking networks with packet buffering at the switch outputs. These have optimal throughput and delay performance. The author considers a switch architecture consisting of parallel plans of low-speed internally blocking switch networks, in conjunction with input and output buffering. This architecture is desirable from the viewpoint of modularity and hardware cost, especially for large switches. Although this architecture is suboptimal, the throughput shortfall may be overcome by adding extra switch planes. A form of input queuing called bypass queuing can improve the throughput of the switch and thereby reduce the number of switch planes required. An input port controller is described which distributes packets to all switch planes according to the bypass policy, while preserving packet order for virtual circuits. Some simulation results for switch throughput are presented     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

Performance of fiber delay‐line buffers in asynchronous packet‐based optical switching networks with wavelength conversion

A major challenge in asynchronous packet‐based optical networks is packet contention, which occurs when two or more packets head to the same output at the same time. To resolve contention in the optical domain, two primary approaches are wavelength conversion and fiber delay line (FDL) buffering. In wavelength conversion, a contending packet can be converted from one wavelength to another in order to avoid conflict. In FDL buffering, contending packets can be delayed for a fixed amount of time. While the performance of wavelength conversion and FDL buffering has been evaluated extensively in synchronous networks with fixed‐sized packets, in this paper, we study the performance of FDL buffers in asynchronous packet‐based optical networks with wavelength conversion. An analytical model is proposed to evaluate the performance in terms of packet loss probability and average delay. Extensive simulation and analytical results show that, with appropriate settings, FDL buffers can perform much better in switches with wavelength conversion than in switches with no conversion. Copyright © 2014 John Wiley & Sons, Ltd.     

采用部分共享光缓存和共享波长转换器的光分组交换节点性能分析

本文研究了采用部分共享缓存(PSB)和共享波长转换器(SWC)的光分组交换节点在自相似流量下分组丢失率和时延与输出光缓存深度、循环共享光缓存的深度和组数以及波长转换器数量之间的关系,并讨论了相关的尺度和规模问题.结果表明,部分共享光缓存和共享波长转换器的光分组交换节点交换结构可以达到很高的性能;采用共享方式可显著减少波长转换器的数量;在保持共享缓存总的深度不变的情况下,适当增加循环共享光缓存组数可以使交换达到更好的性能.     

Using a packet switch for circuit-switched traffic: a queueingsystem with periodic input traffic

Consideration is given to the effects of time-multiplexed stream traffic on the performance of a store-and-forward packet switch. Substantially reducing the amount of buffering in the switch results in only a small probability that an existing circuit will be disrupted during the length of its connection. For example, with a circuit-switched frame of length 1000 and 100% loading, reducing the buffer size from 999 packets to 83 results in only a 10^-6 circuit-disruption probability     

Cost Evaluation of Optical Packet Switches Equipped With Limited-Range and Full-Range Converters for Contention Resolution

Two architectures are proposed for a wavelength-division multiplexed optical packet switch equipped with both limited-range wavelength converters (LRWCs) and shared full-range wavelength converters (FRWCs). The FRWCs are used to overcome the performance degradation in terms of packet loss probability due to the use of LRWCs only. Two different sharing strategies of the FRWCs are considered. In the first architecture, a pool of FRWCs is shared among the arriving packets. In the second one, the sharing is only partial and the packets directed to the same output share a same pool of FRWCs. A probabilistic model is proposed to dimension the number of shared FRWCs so that the same packet loss probability of a switch equipped with only shared FRWCs is guaranteed. After introducing a cost model of the converters depending on the conversion range, we show that the architectures may allow a conversion cost savings on the order of 90%.     

Performances of the Data Vortex switch architecture under nonuniform and bursty traffic

The Data Vortex switch architecture has been proposed as a scalable low-latency interconnection fabric for optical packet switches. This self-routed hierarchical architecture employs synchronous timing and distributed traffic-control signaling to eliminate optical buffering and to reduce the required routing logic, greatly facilitating a photonic implementation. In previous work, we have shown the efficient scalability of the architecture under uniform and random traffic conditions while maintaining high throughput and low-latency performance. This paper reports on the performance of the Data Vortex architecture under nonuniform and bursty traffic conditions. The results show that the switch architecture performs well under modest nonuniform traffic, but an excessive degree of nonuniformity will severely limit the scalability. As long as a modest degree of asymmetry between the number of input and output ports is provided, the Data Vortex switch is shown to handle very bursty traffic with little performance degradation.     

Performance analysis of handover delay and buffer capacity in mobile OpenFlow‐based networks

Software‐defined networking (SDN) is a network concept that brings significant benefits for the mobile cellular operators. In an SDN‐based core network, the average service time of an OpenFlow switch is highly influenced by the total capacity and type of the output buffer, which is used for temporary storage of the incoming packets. In this work, the main goal is to model the handover delay due to the exchange of OpenFlow‐related messages in mobile SDN networks. The handover delay is defined as the overall delay experienced by the mobile node within the handover procedure, when reestablishing an ongoing session from the switch in the source eNodeB to the switch in the destination eNodeB. We propose a new analytical model, and we compare two systems with different SDN switch designs that model a continuous time Markov process by using quasi‐birth–death processes: (1) single shared buffer without priority (model SFB), used for all output ports for both control and user traffic, and (2) two isolated buffers with priority (model priority finite buffering [PFB]), one for control and the other for user plane traffic, where the control traffic is always prioritized. The two proposed systems are compared in terms of total handover delay and minimal buffer capacity needed to satisfy a certain packet error ratio imposed by the link. The mathematical modeling is verified via extensive simulations. In terms of handover delay, the results show that the model PFB outperforms the model SFB, especially for networks with high number of users and high probability of packet‐in messages. As for the buffer dimensioning analysis, for lower arrival rates, low number of users, and low probability of packet‐in messages, the model SFB has the advantage of requiring a smaller buffer size.     

Reservation-based contention resolution mechanism forBatcher-Banyan packet switches

The authors introduce a new method, called ring reservation, to design high-capacity packet switches. Input buffering is used with output port reservations to eliminate packet collisions. They describe a 32×32 prototype packet switch, built as a part of a broadband ISDN prototype, which has a per-port capacity of 30-55 Mbit/s     

Performance analysis of nonblocking packet switch with input andoutput buffers

The performance of nonblocking packet switches such as the knockout switch and Batcher banyan switch for high-speed communication networks can be improved as the switching capacity L per output increases; the switching capacity per output refers to the maximum number of packets transferred to an output during a slot. The N×N switch with L=N was shown to attain the best possible performance by M.J. Karol et al. (1987). Here a N×N nonblocking packet switch with input and output buffers is analyzed for an arbitrary number of L such that 1⩽L⩽N. The maximum throughput and packet loss probability at input are obtained when N=∞     

Traffic performance evaluation of an optical packet switch with multicast operation

We recently proposed a multicast-enabled optical packet switch architecture utilizing multicast modules. In this paper, we evaluate the traffic performance of our earlier proposed packet switch under a hybrid traffic model through simulations. The multicast packets are given higher priority than unicast packets so that only a small number of multicast modules are needed. The results show that the switch can achieve an acceptable packet loss probability in conjunction with a packet scheduling technique.     

All-optical cross-connect using feed-forward optical buffers with and without QoS: an analysis

An analytical model is derived to evaluate the performance of an optical switch using a feed-forward fiber delay line (FDL) per output for contention resolution. Two different forwarding algorithms for the switch are presented and evaluated: a simple forwarding algorithm (SFA) that is easier to implement, and an enhanced algorithm that provides better performance in terms of both packet loss probability and packet delay. The analytical model can be utilized with both packet and burst switching schemes to characterize the performance of the proposed architecture. Results show that the proposed architecture reduces the packet loss probability compared to that without FDLs. Finally, the same architecture is shown to be capable of supporting Quality of Service (QOS).

Multi-wavelength switching in IP optical nodes adopting different buffering strategies

The paper addresses the topic of long-haul optical networking for the provision of large-bandwidth IP services. A class of optical packet switching architectures is considered which adopts an arrayed wavelength grating device as packet router. The architecture performs slotted packet switching operations and fully exploits the wavelength routing capabilities by allowing multi-wavelength switching. Fiber delay lines are used to perform optical packet buffering, which accomplishes either input queueing or shared queueing. Here a thorough performance evaluation is carried out with different buffering configurations and the effect of various switch parameters on traffic performance is studied.     

Wavelength conversion in optical packet switching

A detailed traffic analysis of optical packet switch design is performed. Special consideration is given to the complexity of the optical buffering and the overall switch block structure is considered in general. Wavelength converters are shown to improve the traffic performance of the switch blocks for both random and bursty traffic. Furthermore, the traffic performance of switch blocks with add-drop switches has been assessed in a Shufflenetwork showing the advantage of having converters at the inlets. Finally, the aspect of synchronization is discussed through a proposal to operate the packet switch block asynchronously, i.e. without packet alignment at the input