A new lateral MOS-gated thyristor with controlling base-current

A new lateral MOS-gated thyristor, called the Base-Current-Controlled Thyristor, is described. This device is designed so that most holes at the on-stage reach the P base through the floating P⁺ region adjacent to the P base and the on-state MOSFET. At the turn-off stage, the interruption of the hole current to the P base due to switching off the above MOSFET occurs simultaneously with the conventional turn-off operation. The concept of this device is verified experimentally by using the fabricated lateral device with the external MOSFET. This device exhibits a better trade-off relation between the on-state voltage and the turn-off time compared uith the conventional MOS-gated thyristor     

3100 V, asymmetrical, gate turn-off (GTO) thyristors in 4H-SiC

A 2-mm×2-mm, 4H-SiC, asymmetrical npnp gate turn-off (GTO) thyristor with a blocking voltage of 3100 V and a forward current of 12 A is reported. This is the highest reported power handling capability of 37 kW for a single device in SiC. The 5-epilayer structure utilized a blocking layer that was 50 μm thick, p-type, doped at about 7-9×10¹⁴ cm^-3. The devices were terminated with a single zone junction termination extension (JTE) region formed by ion-implantation of nitrogen at 650°C. The device was able to reliably turn-on and turn-off 20 A (500 A/cm²) of anode current with a turn-on gain (I_K/I_{G, on}) of 20 and a turn-off gain (I_K/I_{G, off}) of 3.3     

Effect of bipolar turn-on on the static current-voltagecharacteristics of scaled vertical power DMOSFET's

The parasitic bipolar transistor inherent in the power vertical Double Diffused MOSFET (DMOSFET) structure can have a significant impact on its performance and reliability. Selectively formed TiSi₂ films on source contacts were used to reduce the contact resistance to n ⁺ source diffusion. These devices exhibit “kinks” in the output I-V characteristics. High contact resistance of TiSi₂ to moderately doped p-body diffusion causes high output conductance. Detailed two-dimensional numerical simulations are used to investigate the effect of the parasitic bipolar transistor on the static characteristics of scaled silicided DMOSFET's. The high contact resistance of TiSi₂-p-body interface leads to a floating potential and causes significant reduction in the MOS gate threshold voltage and results in a premature bipolar turn-on. It is shown that the parasitic bipolar turn-on places an important constraint on the scalability of the device into the submicron regime. A novel self-aligned DMOSFET structure with a shallow diffused p⁺ region is shown to eliminate this effect. Numerical simulations are shown to be in excellent agreement with the measured data at various temperatures     

Ultralow-voltage boron-doped diamond field emitter vacuum diode

A boron-doped diamond field emitter diode with ultralow turn-on voltage and high emission current is reported. The diamond field emitter diode structure with a built-in cap was fabricated using molds and electrostatic bonding techniques. The emission current versus anode voltage of the capped diamond emitter diode with boron doping, sp² content, and vacuum thermal electric (VTE) treatment shows a very low turn-on voltage of 2 V. A high emission current of 1 μA at an anode voltage of less than 10 V can be obtained from a single diamond tip. The turn-on voltage is significantly lower than comparable silicon field emitters     

Fabrication and optical-switching results on the integrated light-triggered and quenched static induction thyristor

An integrated structure of the light-triggered and light-quenched (LTQ) static induction (SI) thyristor is introduced and is fabricated by the combination of the SI thyristor and SI transistor process technology. The device consists of a buried-gate light triggered (LT) SI thyristor and a p,channel surface gate static induction photo-transistor (SIPT). An anode voltage VAKof 500 V at an anode current IAKof 1 A (600 A/cm²: channel current density) is optically switched with a triggering power ofP_{LT} = 11mW/cm²(92 µW) and a quenching power ofP_{LQ} = 11mW/cm²(110 µW) in a turn-on time of 0.7 µs and a turnoff delay time of 1.0 µs. The integrated LTQ SI thyristor is a novel type of self-turn-off power device that is turned on and off by optical means.     

利用CsN3n型掺杂电子传输层改善OLED器件性能的研究

为了能够有效地提高电子的注入和传输能力,改善有机电致发光器件的性能,本文利用CsN₃作为n型掺杂剂,对有机电子传输材料Bphen进行n型电学掺杂,制备了结构为ITO/MoO₃（2 nm）/NPB（50 nm）/Alq₃（30 nm）/Bphen（15 nm）/Bphen：CsN₃（15 nm,x%,x=10,15,20）/Al（100 nm）的器件。实验结果表明,CsN₃是一种有效的n型掺杂剂,以掺杂层Bphen：CsN₃ 作为电子传输层,可以有效地降低电子的注入势垒,改善器件的电子注入和传输能力,从而降低器件的开启电压,同时提高了器件的亮度和发光效率。在掺杂浓度为10%时器件的性能最优,开启电压仅为2.3 V,在7.2 V的驱动电压下,达到最大亮度29 060 cd/m²,是非掺杂器件的2.5倍以上。当驱动电压为6.6 V时,达到最大电流效率3.27 cd/A。而当掺杂浓度进一步提高时,由于Cs扩散严重,发光区形成淬灭中心,造成器件的效率下降。     

On a GaN-Based Light-Emitting Diode With a p-GaN/i-InGaN Superlattice Structure

An interesting GaN-based light-emitting diode (LED) with a ten-period i-InGaN/p-GaN (5-nm/5-nm) superlattice (SL) structure, inserted between a multiple-quantum-well structure and a p-GaN layer, is fabricated and studied. This inserted SL can be regarded as a confinement layer of holes to enhance the hole injection efficiency. As compared with a conventional LED device without the SL structure, the studied LED exhibits better current-spreading performance and an improved quality. The turn-on voltage, at 20 mA, is decreased from 3.32 to 3.14 V due to the reduced contact resistance as well as the more uniformity of carrier injection. A substantially reduced leakage current (10^-7-10^-9 A) and higher endurance of the reverse current pulse are found. As compared with the conventional LED without the SL structure, the significant enhancement of 25.4% in output power and the increment of 5% in external quantum efficiency are observed.     

Turn-on process in 4H-SiC thyristors

Detailed turn-on measurements of 4H-Silicon Carbide (SiC) npnp thyristors are presented for a wide range of operating conditions. Comparisons with similarly-rated silicon and Gallium Arsenide thyristors show a superior rise time and pulsed turn-on performance of SiC thyristors. Rise time for a 400 V blocking voltage, 4 V forward drop (2.8×10³ A/cm²) SiC thyristor has been found to be of the order of 3-5 ns. Pulsed turn on measurements show a residual voltage of only 50 V when a current density of 10⁵ A/cm² (35 A) was achieved in 20 ns     

Investigation of temperature-dependent characteristics of ann+-InGaAs/n-GaAs composite doped channel HFET

The temperature-dependent characteristics of an n⁺-InGaAs/n-GaAs composite doped channel (CDC) heterostructure field-effect transistor (HFET) have been studied. Due to the reduction of leakage current and good carrier confinement in the n ⁺-InGaAs/n-GaAs CDC structure, the degradation of device performances with increasing the temperature is insignificant. Experimentally, for a 1×100 μm² device, the gate-drain breakdown voltage of 24.5 (22.0) V, turn-on voltage of 2.05 (1.70) V, off-state drain-source breakdown voltage of 24.4 (18.7) V, transconductance of 161 (138) mS/mm, output conductance of 0.60 (0.60) mS/mm, and voltage gain of 268 (230) are obtained at 300 (450) K, respectively. The shift of V_th from 300 to 450 K is only 13 mV. In addition, the studied device also shows good microwave performances with flat and. wide operation regime     

A 550 V Isolated Channel Base Resistance Controlled Thyristor(ICBRT)

In this paper we report a 550 V Isolated Channel Base Resistance Controlled Thyristor (ICBRT), which incorporates a heavily doped p-type diffusion at the edges of the p-base of the conventional Base Resistance Controlled Thyristor (BRT) to improve its turn-off capability. The desirable gate controlled turn-on and turn-off features of the BRT are retained in this new device along with separate turn-on and turn-off regions. A 70% improvement in the maximum controllable current density during resistive turn-off over the conventional BRT has been demonstrated in numerical simulations and experimental measurements     

Functional integration of the light-triggered static induction thyristor and the static induction phototransistor

An integrated structure of the Light-Triggered and Light-Quenched Static Induction (LTQ SI) thyristor is introduced and is fabricated by the combination of the SI thyristor and the static-induction-transistor (SIT) process technology. The device consists of a buried-gate light-triggered (LT) SI thyristor and a p-channel surface-gate static induction phototransistor (SIPT). The analog voltage VAKof 250 V at the anode Current IAKof 2 A (600 A/cm²: channel current density) is optically switched with a triggering power ofP_{LT} = 8.8mW/cm²(150 µW) and a quenching power ofP_{LQ} = 8.8mW/cm²(88 µW) in a turn-on time of 1.2 µs and a turn-off delay time of 1.2µs. The integrated LTQ SI thyristor is a novel type of the self-turn-off power switching device which is turned on and off by optical means.     

High-Gain Low Turn-On Voltage AlGaAs/GaAsNSb/GaAs Heterojunction Bipolar Transistors Grown by Molecular Beam Epitaxy

AlGaAs/GaAsNSb heterojunction bipolar transistors (HBTs) with low turn-on voltage have been fabricated. The turn-on voltage of the device fabricated from an as-grown sample is ~180 mV lower than that of a conventional AlGaAs/GaAs HBT. The effect of rapid thermal annealing on device performance is an increase in the gain from ~8.5 to ~20. However, the knee voltage of the annealed sample (~3 V), as well as the turn-on voltage, is also higher compared with that of the as-grown sample (~1.5 V).     

A 30 V Self-Aligned Metal/Poly-Si Replacement Gate Planar DMOS for DC/DC Converters

In this letter, a novel self-aligned metal/poly-Si gate planar double-diffused MOS (DMOS) is proposed and demonstrated for high-switching-speed and high-efficiency dc/dc converter applications. The self-aligned metal/poly-Si gate is realized by a replacement gate technology. The fabricated metal/poly-Si gate planar DMOS has a breakdown voltage of 36 V and a threshold voltage of 2.1 V. The gate sheet resistance of the metal/poly-Si gate is around 0.2 Omega/square, which is 50 times lower than that of the polysilicon gate. The low sheet resistance reduces the switching time as well as the power loss of the device during switching. For a device with a drain current of 69 A/cm², the turn-on and turn-off times are reduced from 29 to 25 ns and from 36 to 31 ns, respectively. The turn-on and turn-off switching energy losses are reduced by 22% and 15%, respectively     

550 V, N-channel emitter switched thyristors with anatomic-lattice-layout (ALL) geometry

Experimental and simulation results for a 550 V, Atomic-Lattice-Layout (ALL) cell Emitter Switched Thyristor are reported here for the first time and compared to the conventional stripe cell geometry. It is shown that the ALL cell design improves the maximum gate controllable current density of the Emitter Switched Thyristor by 40%, with a small loss in forward performance at current densities less than 400 A/cm²     

A high-current and high-temperature 6H-SiC thyristor

A 6H-SiC thyristor has been fabricated and characterized. A forward breakover voltage close to 100 V and a pulse switched current density of 5200 A/cm² have been demonstrated. The thyristor is shown to operate under pulse gate triggering for turn-on and turn-off, with a rise time of 43 ns and a fall time of less than 100 ns. The forward breakover voltage is found to decrease by only 4% when the operating temperature is increased from room temperature to 300°C. It is found that anode ohmic contact resistance dominates the device forward drop at high current densities     

Design methodology and simulation tool for floating ring termination technique

A new methodology to optimize the design of floating ring (FR) termination technique for high voltage device is presented. The basic idea is to simulate the blocking capability of the structure with only one guard ring and then extend the results to a multiple FR system. A second advantage of our method is to include the ring width in the optimization process. The effectiveness and efficiency of our methodology is illustrated by optimizing a FR structure with a junction depth x_j=5 μm and Si substrate doping 2·10¹⁴ cm⁻³. A seven rings structure is optimized giving 85% efficiency in respect to the ideal plane parallel junction breakdown voltage V_BD=840 V. The simulation results are generated by the user-oriented simulation program POWER2D for studying the voltage handling capability of arbitrary shaped power semiconductor devices. A special algorithm is implemented ensuring very fast and automatic search of the breakdown via the ionization integrals calculus. An efficient numerical algorithm to drastically reduce the number of iterations when adjusting the quasi-Fermi potential of the floating rings has also been developped     

Comparison of GaN p-i-n and Schottky rectifier performance

The performance of GaN p-i-n and Schottky rectifiers fabricated on the same wafer was investigated as a function of device size and operating temperature. There was a significant difference in reverse breakdown voltage (490 V for p-i-n diodes; 347 V for the Schottky diodes) and forward turn-on voltage (~5 V for the p-i-n diodes; ~3.5 V for the Schottky diodes). Both types of device showed a negative temperature coefficient for reverse breakdown, with value -0.34±0.05 V·K^-1     

A Stable Field-Emission Light Source With ZnO Nanoemitters

A field-emission cathode is fabricated with ZnO tetrapodlike nanoemitters. With a simple planar triode structure, a cathodoluminescent light source has been investigated. Because of the characteristics of surface-conduction electron-emission planar triode, this cathodoluminescent light source shows a very good performance. As experimental results show, the turn-on electric field is about 1 V/mum, whereas the current density is 1 muA/cm². The threshold electric field is 1.6 V/mum, whereas the current density is 1 mA/cm². When a pulse voltage with 4% duty cycle is applied on the gate electrode, the fluctuation of anode current is smaller than 15 % during 200 h.     

Analysis and optimisation of the trench gated emitter switched thyristor

The performance of the trench gated emitter switched thyristor (TEST) is investigated by numerical simulations. More specifically, the influence of the N⁺ floating emitter on the forward voltage drop and forward-biased safe operating area (FBSOA) is studied in detail. It is demonstrated that, by reducing the doping of this region, the FBSOA of the TEST can be significantly increased with a negligible degradation of the forward voltage drop V_CE(SAT). Moreover, a new cathode design is proposed for the TEST by removing the connection between the two P base regions and leaving one of them floating. By doing so, the snap-back from the static turn-on is removed, and the forward voltage drop is improved even for a lower doping of the N⁺ floating emitter.     

Turn-off operation of a MOS-gate 2.6 kV 4H–SiC gate turn-off thyristor

The turn-off operation of a 4H–SiC gate turn-off thyristor (GTO) with 2.6 kV breakover voltage has been investigated using an external Si-MOSFET as a gate-to-emitter shunt (MOS-gate mode), in the temperature interval 293–496 K. The maximum cathode current density j_cmax that can be turned off in such a mode decreases from 1850 A/cm² at 400 K to 700 A/cm² at 496 K. The room temperature j_cmax value is estimated to be about 3700 A/cm². The above j_cmax values are essentially higher than those observed when turning this thyristor off in the conventional GTO mode. Turn-off transients in the MOS-gate mode have been studied in both quasi-static and pulse regimes. Temperature dependencies of the turn-on and turn-off times, as well as those of the turn-on and turn-off energy losses have been measured. The upper switching frequency of the GTO is estimated to be about 700 kHz.