3.1～10.6 GHz低功耗超宽带低噪声放大器

采用TSMC 0.18 μm CMOS工艺库,设计并验证了一种应用于3.1～10.6 GHz频段的超宽带低噪声放大器。该放大器分为两级:采用跨导增强技术的共栅结构作为输入级,实现了输入阻抗匹配,提高了增益并降低了噪声;第二级是放大输出级,由两个共源放大管和源跟随器缓冲管构成,并采用两级电流复用配置将它们连接在一起,不但对信号进行了二次放大,降低了功耗,而且实现了输出匹配。仿真结果表明,在3.1～10.6 GHz频带范围内,放大器增益为14.8 dB,增益平坦度为SymbolqB@0.6 dB,噪声系数介于2.9～4.5 dB,输入和输出的回波损耗均优于-11 dB,1 dB压缩点为-20.8 dBm,在1.8 V电压下,静态功耗仅为8.99 mW。     

SiGe HBT超宽带低噪声放大器设计

采用ADS软件设计并仿真了一种应用于UWB标准的低噪声放大器。该低噪声放大器基于JAZZ 0.35μmSiGe工艺,工作带宽为3.1～10.6GHz。电路的输入极采用共发射极结构,利用反馈电感来进行输入匹配,第二级采用达林顿结构对信号提供合适的增益。使用ADS2006软件进行设计、优化和仿真。仿真结果显示,在3.1～10.6GHz带宽内,放大器的电源电压在3.3V时,噪声系数低于2.5dB,增益大于24dB,功耗为28mV,输出三阶交调为17dBm。     

3.1～5.2GHz超宽带可变增益低噪声放大器设计

低噪声放大器是超宽带接收机系统中最重要的模块之一,设计了一种可应用于3.1～5.2GHz频段超宽带可变增益低噪声放大器。电路输入级采用共栅结构实现超宽带输入匹配,并引入电流舵结构实现了放大器的可变增益。仿真基于TSMC 0.18μm RF CMOS工艺。结果表明,在全频段电路的最大功率增益为10.5dB,增益平坦度小于0.5dB,噪声系数小于5dB,输入反射系数低于-15dB,在1.8V电源电压下,功耗为9mW。因此,该电路能够在低功耗超宽带射频接收机系统中应用。     

增益可调宽带CMOS低噪声放大器设计

设计了一种应用于超宽带系统中的可变增益宽带低噪声放大器。电路中采用了二阶巴特沃斯滤波器作为输入和输出匹配电路;采用了两级共源共栅结构实现电路的放大,并通过控制第二级的电流,实现了在宽频带范围内增益连续可调;采用了多栅管(MGTR),提高了电路的线性度;设计基于SMIC 0.18μm CMOS工艺。仿真结果显示,在频带3~5 GHz的范围内最高增益17 dB,增益波动小于1.8 dB,输入和输出端口反射系数分别小于-10 dB和-14 dB,噪声系数nf小于3.5 dB,当控制电压Vctrl=1.4 V时,IIP3约为2 dBm,电路功耗为16 mW。     

利用噪声抵消技术设计低噪声放大器

采用ADS软件设计并仿真了一种应用于WiMax2标准的低噪声放大器。该低噪声放大器基于TSMC 0.13μmCMOS工艺,工作带宽为2.3 GHz~2.7GHz。在电路设计中采用噪声抵消技术降低CMOS管的电流噪声。使用共栅极结构进行输入匹配,使用电容进行输出匹配。偏置电路采用电流镜原理。使用ADS2006软件进行设计、优化和仿真。仿真结果显示,在2.3 GHz~2.7GHz带宽内,放大器的电源电压在1.2V时,噪声系数低于1.96dB,增益大于21.8dB,整个电路功耗为9mW。     

一种0.13 μm CMOS K波段LNA

基于0.13 μm CMOS工艺,设计了一种工作于K波段的低噪声放大器。输入匹配采用一种改良π型匹配网络,输出匹配采用L+π型匹配网络,避免了电容击穿的风险和源端大电感的引入。电路使用级间L型匹配的方式,利用第一级电路的输出寄生电容和第二级电路的输入寄生电容,有效地提高了电路的增益,降低了噪声。仿真结果表明,该低噪声放大电路为单电源1.5 V供电,在27 GHz频率处的增益为27 dB,噪声系数为3.75 dB,输入回波损耗和输出回波损耗分别为－11.1 dB和－20.5 dB。     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。     

一种0.13 μm CMOS K波段宽带功率放大器

基于0.13 μm CMOS工艺,采用多频点叠加的方式,设计了一种K波段宽带功率放大器。输入级采用晶体管源极感性退化方式,实现了宽带输入匹配。驱动级采用自偏置共源共栅放大器,为电路提供了较高的增益。输出级采用共源极放大器,保证电路具有较高的输出功率。后仿真结果表明,在26 GHz处,该功率放大器的增益为22 dB,－3 dB带宽覆盖范围为22.5~30.5 GHz,输出功率1 dB压缩点为8.51 dBm,饱和输出功率为11.6 dBm,峰值附加功率效率为18.7%。     

一种用于采保电路的宽带高增益放大器的设计

分析了跨导运算放大器的电路结构,采用两级放大电路,考虑到全差分结构中要使用共模反馈,用共源共基和共源共栅电路来实现电路的设计.同时对部分性能指标进行了优化,其中包括增益非线性引入的误差和不完全建立误差.设计了一种宽带高增益跨导放大器,利用0.35 μm Bi CMOS工艺条件下,Spectre仿真得到运算放大器的开环增益大于60 dB,单位增益带宽可达2.1 GHz,输出摆幅能达到1.5 V.     

低电压低功耗宽带CMOS低噪声放大器的设计

设计了一种应用于宽带(0.8～3.0GHz)接收机的低电压低功耗低噪声放大器。该放大器以折叠的共源共栅结构为基础,采用噪声抵消结构,通过两条并联的等增益支路来抵消匹配器件在输出端所产生的噪声,实现输入阻抗匹配和噪声优化。电路采用0.18μm CMOS工艺,利用Cadence软件进行设计和仿真。结果表明,该低噪声放大器在0.8～3.0GHz带宽范围内噪声系数(NF)小于3.2dB,电压增益(S21)在17.6～18.5dB之间,S11小于-12dB,S22小于-20dB,在0.8V电源电压下,功耗为9.7mW,版图面积为0.18mm2。     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-/spl mu/m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7/spl plusmn/0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

0.18 μm 3.1-10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7± 17.4 ps group-delay

A3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn17.4 ps across the whole band) using standard 0.18 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S₁₁) of -9.7 to -19.9 dB, output return loss (S22) of-8.4 to -22.5 dB, flat forward gain (S21) 11.4 plusmn0.4 dB, reverse isolation (S12) of -40 to -48 dB, and noise figure of 4.12-5.16 dB over the 3.1-10.6 GHz band of interest. A good 1 dB compression point (Pi dB) of -7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681 x 657 mum excluding the test pads.     

2.5 dB NF 3.1-10.6 GHz CMOS UWB LNA with small group-delay variation

A 3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay variation is only plusmn 16.7 ps across the whole band) using standard 0.13 mum CMOS technology is reported. To achieve high and flat gain and small group-delay variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA achieved input return loss (S₁₁) of -17.5 to -33.6 dB, output return loss (S₂₂) of -14.4 to -16.3 dB, flat forward gain (S₂₂) of 7.92 plusmn 0.23 dB, and reverse isolation (S₁₂) of -25.8 to -41.9 dB over the 3.1-10.6 GHz band of interest. A state-of-the-art noise figure (NF) of 2.5 dB was achieved at 10.5 GHz.     

A Low-Noise Amplifier With Tunable Interference Rejection for 3.1- to 10.6-GHz UWB Systems

An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-$mu$m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5–6.2 dB with bandwidth of 3.1–10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is ${-} $11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.      

一种采用有源电感的可调增益小面积超宽带低噪声放大器

设计了一款采用可调谐有源电感（TAI）的可调增益的小面积超宽带低噪声放大器(LNA),输入级采用共基极结构,输出级采用射随器结构,分别实现了宽带输入和输出匹配;放大级采用带有反馈电阻的共射共基结构以取得宽的带宽,并采用TAI作负载,通过调节TAI的多个外部偏压使LNA的增益可调。结果表明,该LNA在2~9GHz的频带内,通过组合调节有源电感调节端口的偏压可实现S21在16.5~21.1dB的连续可调;S11小于-14.7dB;S22小于-19.3dB;NF小于4.9dB;芯片面积仅为0.049mm2。