Molybdenum gate MOS applied to an AM/FM digital frequency synthesizer

An n-channel molybdenum self-aligned gate MOS technology has been developed and applied to an AM/FM digital frequency synthesizer. A high-frequency programmable divider operating at 180 MHz has been achieved by the use of molybdenum, low parasitic capacitance structures and zero-threshold MOS transistors, while maintaining conventional design rules. Molybdenum gate MOS has enabled the realization of a single-chip system, which consists of a directly programmable divider for the AM/FM local oscillators, a reference counter, a phase comparator, a circuit for dial tuning, and memories for storing the frequencies for 16 stations. A differential comparator has been fabricated on the LSI chip to simplify digital tuning in the receiver.     

An MOS integrated circuit for digital filtering and level detection

An LSI circuit for digital signal processing has been designed and manufactured in 5 V n-channel MOS technology. Its main functions are to implement digital filters of the cascaded biquadratic form and to perform level detection operations. The frequency response of the filter is controlled by coefficients supplied from an external memory. The device, known by the acronym FAD (filter and detect), operates from a single-phase clock and can process up to 64000 samples/s at the maximum permissible clock rate of 2048 kbit/s. Although FAD was designed for one particular requirement, it has sufficient flexibility for use in a variety of application.     

A compatible NMOS, CMOS metal gate process

An MOS LSI technology is presented, which allows the efficient fabrication of n-MOS and CMOS circuits on the same chip, a capability, which has become highly desirable in view of recent advances in circuit design, particularly analog-digital interfaces. The process starts from a p-type substrate. An n-well is formed by ion implantation. An additional implantation simultaneously sets the p-channel and n-channel threshold voltages as well as the field threshold above the substrate. The implanted field provides high density and simple processing. A third implantation step adjusts the threshold voltage of the n-channel depletion load transistor. Supply voltages up to 20 V are possible. Process modeling data are presented both by theoretical consideration and the measurement of actual profiles of the well and threshold dependence on energy, dose, and drive-in conditions. Distributions of the electrical parameters are rather narrow with standard deviations of thresholds <150 mV. Transconductance constants are typically 9 and 29 µA . V^-2for p-and n-channel transistors, respectively. CMOS inverter gain is 250 for channel lengths of 10 and 25 µm, respectively.     

Current Status of Large Scale Integration Technology

The current status of large scale integration (LSI) technology is reviewed, with emphasis on developments made during the past year. Problem areas and solution approaches are emphasized, Four LSI technologies are considered as follows. 1) LSI bipolar chip technology (100 percent yield over chip area) reviews progress toward increasing the cornplexit y level on semiconductor chips. Conclusions of a Texas Instruments study of yie!d versus chip area are discussed, and a forecast is made of complexity levels for logic and memory. Several master-slice customization programs now under development in industry are reviewed. 2) LSI full-slice technology (discretionary wiring) is discussed for read-write and read-only memory of 1600 bits per slice and customized logic of 100 to 250 gates per slice. 3) LSI MOS technology is reviewed emphasizing progress in speed improvements and area reduction through development of four-phase ratioless circuitry. Technological factors which govern MOS speed are discussed. 4) LSI hybrid technology is briefly discussed. The paper concludes with a discussion of complexity versus cost, perfommce, and reliability for various LSI technologies. The problem of selecting an optimum LSI technology for a given application is discussed by consideration of several specific examples.     

Femtojoule high speed planar GaAs E-JFET logic

An integrated inverter stage operating in the gigabit range at a static power dissipation of 100 µW was built for future use in LSI logic circuits. Planar gallium arsenide technology was employed using selective ion-implanted enhancement mode junction field-effect transistors (E-JFET) having 3-µm gate lengths. A nine-stage ring oscillator served as a test vehicle to assess the speed-power product for digital applications. A theoretical analysis shows the transistor operates during the switching transient in the saturation regime, notwithstanding steady-state operation in the linear regime. When the transistor is switched off, the transient response is governed by the load resistance and the input capacitance of the subsequent stage. Means of reducing the switching time by increasing the supply voltage, nonlinear load devices, an output buffer stage, and reduction of gate length and width are described. Directly coupled E-JFET logic does not require level shifting, and, therefore, offers advantages over depletion-mode gallium arsenide MESFET logic by reducing the number of circuit elements per gate. Projected gallium arsenide E-JFET LSI logic circuits will surpass silicon-based bipolar logic with respect to both speed and power, and n-channel silicon MOS logic with respect to speed.     

Double ion implanted V-MOS technology

An n-channel double ion implanted (or diffused] lateral V-MOS structure (D-V-MOS) for LSI digital application is presented. The effective channel is formed by the vertical difference in an n-type and a p-type impurity profile on a high resistive p-type substrate through a V-groove technique. Thus the threshold voltage and effective channel length of the D-V-MOS can be directly and accurately controlled by ion implantation. Very short-channel length (0.1 to 0.2 /spl mu/m) MOS devices with good electrical characteristics can thus be realized. A simple fabrication process with 5 masking steps for an n-channel self-isolated self-aligned enhancement/depletion (E/D) D-V-MOST device is presented. The fabrication procedures are described. Special features associated with the V structure are discussed. The short-channel effect is treated. It is found that the substrate sensitivity due to source-substrate biasing for a short-channel D-V-MOS is reduced significantly, even with a 1000-/spl Aring/ gate oxide thickness.     

A 1-Mbit DRAM with 33-MHz serial I/O ports

High-speed operation, a 33-MHz serial cycle, and a 10-ns serial data access time have been realized by internal serial/parallel conversion circuits, a newly designed I/O controller circuit, new dynamic register circuits, a divided sensing method, and an optimized layout design. The chip is fabricated with a 1.2-/spl mu/m double-level polysilicon and double-level aluminium n-channel MOS process technology. An optimized interlevel insulator realizes equivalent first- and second-level aluminium pitches for a compact chip design. The chip size is 5.88/spl times/11.2 mm/SUP 2/. This memory has high-speed input and output capability as well as random accessibility. These features are suitable for TV and VCR frame-memory-system applications.     

A 920 gate DSA MOS masterslice

A DSA MOS (diffusion self-aligned MOS) masterslice circuit with up to 920 gates and a delay of 3 ns per gate has been developed for random logic computer circuits, utilizing the performance and economical advantages of the LSI masterslice approach. To attain high packing density and high speed with conventional design rules, the DSA MOSFET technology has been used for the basic device. The chip comprises 50 by 16 gate cells and 116 input/output buffers. This LSI chip is two to three times better than bipolar S-TTL in packing density and is comparable in propagation delay time. As an example of an LSI device obtained through customized metallization, an 8 bit ALU is described which has an average delay time of 3 ns and a power dissipation of 3 W.     

An advanced MOS-IC process technology using local oxidation ot oxygen-doped polysilicon films

An O-POS (oxygen-doped polysilicon) film, deposited directly on silicon, is oxidized locally to create an active gate area. The electrical properties for the active gate area are the same as conventional p- and n-channel MOS devices, but the field area has an extremely high threshold voltage for both p- and n-type silicon substrates. The electrical properties in metal/oxidized O-POS/silicon and metal/oxide/O-POS/silicon structures have been investigated while varying the O-POS film thickness, oxygen concentration, local oxidation time, and silicon substrate resistivity. According to these basic studies, it is proposed that the high density of trapping centers existing in O-POS film is responsible for the high field threshold voltage. A applications of this process technology, a silicon-gate CMOS integrated circuit, and a high voltage n-channel MOS device are discussed.     

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.     

IC implementations of signal-processing systems: an overview

A short review of the principal analog MOS basic building blocks is followed by a discussion of several representative LSI signal-processing circuits that combine analog and digital functions on the same chip. An echo-canceller speech-synthesizer IC, character-recognition circuit for reading wands, and beam-former circuit are implemented with MOS technology and discussed in detail. An example of I/SUP 2/L technology is presented in the form of a data-transmission IC. The evolution toward more complex, dedicated, signal-processing devices is briefly discussed in terms of the technology and engineering requirements.     

A 256-channel C/SUP 2/MOS LSI time-switch using shift-register pipeline multiplexer

SOS technology has been used to retain the pipeline processing speed advantage by controlling the capacitance of on-chip lines that must be long to provide 256-channel operation. Clocked CMOS (C/SUP 2/MOS) circuits have been used to avoid clock-skew problems. A 1.5-/spl mu/m C/SUP 2/MOS/SOS technology has made it possible to integrate 900 transistors into a 4.0/spl times/2.4-mm/SUP 2/ area, and to realize a 256-channel time-switch LSI, with a 15-ns typical output delay time and a 300-mW power dissipation during 25-MHz operation.     

A new self-aligning poly-contact technology for MOS LSI

A new self-aligning contact technology suitable for high density MOS LSI is proposed. This technology includes the following steps: 1) coating the polysilicon gate and interconnection areas by the photosensitive resist and baking it into polymalization. With an appropriate viscosity, resist thickness becomes thinner only above the polysilicon areas; and 2) removing selectively the thinned parts of the resist above the polysilicon areas using photo engraved openings of newly coated resist as a mask. This technology is applicable to the conventional Si-gate MOS processes and especially useful for short-channel MOSFET devices because it does not require a high temperature treatment that greatly spreads out the implanted doses compared with the conventional self-aligning contact technology. The high potential of this technology for MOS LSI is verified by the good yield and the high performance of the CMOS PLL (phase-locked-loop) LSI.     

H-MOS reliability

H-MOS is a new high-performance n-channel technology with a 1-pJ speed power product. This technology is the result of scaling MOS device dimensions. The effect of thinner oxide integrity and hot electron injection are investigated. A screening technique for thin oxides using high-voltage stressing is presented. Threshold shifts due to hot electron injection were observed to be less than 1 mV. Operating lifetest data predict a failure rate of 0.017 percent/1000 h on 4K static RAM's built on H-MOS.     

A single-chip digital signal processor for telecommunication applications

A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The authors describe the design concept, architecture, instructions, device design, and application techniques.     

A high-speed 16-kbit n-MOS random-access memory

This paper presents one version of a high-speed 16-kbit dynamic MOS random-access memory (RAM). This memory utilizes a one transistor cell with an area of 22/spl times/36 /spl mu/m/SUP 2/ which is fabricated using advanced n-channel silicon-gate MOS technology (5-/spl mu/m photolithography). The main feature of the design is a sense circuitry scheme, which allows a high speed (read access time of 200 ns) with low-power dissipation (600 mW at the 400-ns cycle time). The fully decoded memory is fabricated on a 5/spl times/7 mm/SUP 2/ chip and is assembled in a 22-lead ceramic dual-in-line package.     

An integrated NMOS operational amplifier with internal compensation

An internally compensated differential operational amplifier is described which has been fabricated using n-channel Al-gate MOS technology. Only enhancement mode devices are used, and the circuit has been designed so that its performance is insensitive to process parameters.     

FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's

Processing steps of FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's are presented, FIPOS technology realizes a silicon-on-insulator structure, utilizing thick porous oxidized silicon and donors produced by proton implantation. New processing steps are proposed which provides small surface step and are suitable for LSI fabrication. Formation conditions of thick porous oxidized silicon are established by density control technique for porous silicon using a newly developed anodization system. CMOS devices are fabricated in isolated silicon layers and it is shown that the characteristics of n-channel and p-channel MOSFETS's are sufficient for application to CMOS LSI's. A FIPOS/CMOS logic array with 1.3K gate is successfully fabricated, which shows a higher speed and lower power dissipation than the gates fabricated by bulk CMOS technology. These results indicate that FIPOS technology is very useful for realizing high-performance CMOS LSI's.     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.