电极用金属的功函数对OLED发光性能的影响

OLED是一种主动发光器件，影响器件发光性能的因素很多，如电子流与空穴流间的平衡、发光层内电子与空穴的有效复合、外部注入非平衡载流子的能力等。外部注入非平衡载波子的能力与金属－半导体的界面特性有关。本文基于热电子发射理论论述了电极用金属的功函数与非平衡载流子注入的关系，说明其对OLED发光性能的影响。     

Study of single- and dual-channel designs for high-performance strained-Si-SiGe n-MOSFETs

Results comparing strained-Si-SiGe n-channel MOSFET performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates are presented. Device fabrication used high thermal budget processes and virtual substrates were not polished. Mobility enhancement factors exceeding 1.6 are demonstrated for both single-and dual-channel device architectures compared with bulk-Si control devices. Single-channel devices exhibit improved gate oxide quality, and larger mobility enhancements, at higher vertical effective fields compared with the dual-channel strain-compensated devices. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si/sub 0.7/Ge/sub 0.3/ buried channel layer.     

Research progress of Si-based germanium materials and devices

Si-based germanium is considered to be a promising platform for the integration of electronic and photonic devices due to its high carrier mobility, good optical properties, and compatibility with Si CMOS technology. However, some great challenges have to be confronted, such as: (1) the nature of indirect band gap of Ge; (2) the epitaxy of dislocation-free Ge layers on Si substrate; and (3) the immature technology for Ge devices. The aim of this paper is to give a review of the recent progress made in the field of epitaxy and optical properties of Ge heterostructures on Si substrate, as well as some key technologies on Ge devices. High crystal quality Ge epilayers, as well as Ge/SiGe multiple quantum wells with high Ge content, were successfully grown on Si substrate with a low-temperature Ge buffer layer. A local Ge condensation technique was proposed to prepare germanium-on-insulator (GOI) materials with high tensile strain for enhanced Ge direct band photoluminescence. The advances in formation of Ge n⁺p shallow junctions and the modulation of Schottky barrier height of metal/Ge contacts were a significant progress in Ge technology. Finally, the progress of Si-based Ge light emitters, photodetectors, and MOSFETs was briefly introduced. These results show that Si-based Ge heterostructure materials are promising for use in the next-generation of integrated circuits and optoelectronic circuits.     

基于SiGe虚拟衬底的低场迁移率提升140%的应变Si沟道NMOS器件 Cui Wei(崔伟)1,2,Tang Zhaohuan(唐昭焕)2, Tan Kaizhou(谭开洲)2, Zhang Jing(张静)2,

本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。     

GaAs/Ge太阳能电池电极银镀层结合力的研究

采用自制的LP-MOCVD设备,在Ge衬底外延生长出GaAs电池结构,并对电池结构片进行了后工艺制作,同时对电极制作中银镀层结合力的影响因素进行了研究。研究结果表明选择带电入池,无冲击电流方式时,可增强银镀层的结合力。同时采用扫描电子显微镜(SEM)和电子微探针对n型Ge衬底上AuGeNi背电极不同层面的成分进行了分析测试,测试数据表明钨污染将会使银镀层结合力变差。     

SiGe-Channel Confinement Effects for Short-Channel PFETs With Nonbandedge Gate Workfunctions

Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an analogous manner to ultrathin-body approaches. Gate workfunction requirements for thin-SiGe-channel p-type field effect transistors are therefore relaxed substantially more than what is expected from a simple observation of the difference between gate and channel workfunctions. In particular, thin-SiGe channels are shown to enable cost-effective high-performance bulk CMOS technologies with a single gate workfunction near the conduction bandedge. Buried channel, gate workfunction, metal gate, SiGe-channel confinement effects, SiGe-channel MOSFET, silicon germanium, ultrathin-body (UTB).     

Threshold voltage roll-up/roll-off characteristic control insub-0.2-μm single workfunction gate CMOS for high-performance DRAMapplications

Threshold voltage (V_t) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-μm single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N₂ implant prior to gate oxidation is important to reduce V_t roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V_t roll-off characteristics. Finally, the impact of halo implant on V_t variation in sub-0.2-μm buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V_t variation in sub-0.2-μm single workfunction gate pFET     

Single‐Crystal Germanium Growth on Amorphous Silicon

Growing single‐crystal semiconductors directly on an amorphous substrate without epitaxy or wafer bonding has long been a significant fundamental challenge in materials science. Such technology is especially important for semiconductor devices that require cost‐effective, high‐throughput fabrication, including thin‐film solar cells and transistors on glass substrates as well as large‐scale active photonic circuits on Si using back‐end‐of‐line CMOS technology. This work demonstrates a CMOS‐compatible method of fabricating high‐quality germanium single crystals on amorphous silicon at low temperatures of <450 °C. Grain orientation selection by geometric confinement of polycrystalline germanium films selectively grown on amorphous silicon by chemical vapor deposition is presented, where the confinement selects the fast‐growing grains for extended growth and eventually leads to single crystalline material. Germanium crystals grown using this method exhibit (110) texture and twin‐mediated growth. A model of confined growth is developed to predict the optimal confining channel dimensions for consistent, single‐crystal growth. Germanium films grown from one‐dimensional confinement exhibit a 200% grain size increase at 1 μm film thickness compared to unconfined films, while 2D confinement growth achieved single crystal Ge. The area of single crystalline Ge on amorphous layers is only limited by the growth time. Significant enhancement in room temperature photoluminescence and reduction in residual carrier density have been achieved using confined growth, demonstrating excellent optoelectronic properties. This growth method is readily extensible to any materials system capable of selective non‐epitaxial deposition, thus allowing for the fabrication of devices from high‐quality single crystal material when only an amorphous substrate is available.     

SiGe CMOS结构模拟分析

提出一种新的SiGe CMOS结构,用Medici软件对该结构进行二维模拟,分析应变SiGe层、弛豫SiGe层中Ge组份,δ层掺杂浓度以及Si"帽"层厚度等结构参数对SiGe CMOS电学性能的影响.最后,给出该结构组成的反相器传输特性模拟结果.     

TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (NA), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.     

High-performance strained-SOI CMOS devices using thin film SiGe-on-insulator technology

We have developed high-performance strained-SOI CMOS devices on thin film relaxed SiGe-on-insulator (SGOI) substrates with high Ge content (25%) fabricated by the combination of separation-by-implanted-oxygen (SIMOX) and internal-thermal-oxidation (ITOX) techniques without using SiGe buffer structures. The maximum enhancement of electron and hole mobilities of strained-SOI devices against the universal mobility amounts to 85 and 53%, respectively. On the other hand, we have also observed the reduction of carrier mobility in a thinner strained-Si layer or at higher vertical electric field conditions. For the first time, we have demonstrated a high-speed CMOS ring-oscillator using strained-SOI devices, and its improvement amounts to 63% at the supply voltage of 1.5 V, compared to control-SOI CMOS.     

Molecular beam epitaxy passivation studies of Ge and III–V semiconductors for advanced CMOS

Future CMOS technologies will require the use of substrate material with a very high mobility in order to fulfil the performance requirements. Therefore, combination of Ge p-MOS with n-MOS devices made out of high mobility III/V compounds, such as GaAs, has recently received some attention for its possible use in advanced CMOS applications. In this work, the physical, chemical and electrical properties of Al₂O₃ high-κ oxide deposited on Ge and GaAs, using Molecular Beam Deposition (MBD) technique, have been investigated.     

Mobility enhancement in dual-channel P-MOSFETs

Hole mobility is characterized in P-MOSFETs with a layered substrate consisting of tensile strained Si cap on a compressively strained Si/sub 0.4/Ge/sub 0.6/ buried layer grown pseudomorphically to a relaxed Si/sub 0.7/Ge/sub 0.3/ virtual substrate. Besides the expected mobility enhancement in the strained Si cap and in the buried Si/sub 0.4/Ge/sub 0.6/ layer, a second peak in mobility versus total inversion carrier areal density curve was observed under strong inversion conditions in thin Si-cap layer samples. Qualitatively, this reversed mobility trend can be correlated to the transition of inversion conduction from the buried layer to the surface layer, but quantitative analysis reveals that the surface layer mobility in thin Si-cap samples needs to be substantially larger than that in thick-cap samples, if it can be assumed that mobility is a function of transverse field. Further analysis found that, if it is assumed that mobility is a function of inversion carrier density, measured mobility curves can be matched consistently with a single set of mobility-carrier-density relationship.     

The Effect of an Yttrium Interlayer on a Ni Germanided Metal Gate Workfunction in SiO2/HfO2

In this letter, the tuning of a nickel fully germanided metal gate effective workfunction via a hyperthin yttrium (Y) interlayer at the bottom of the metal electrode was demonstrated on both SiO₂ and HfO₂. By varying the Y interlayer thickness from 0 to 9.6 nm, a full range of workfunction tuning from 5.11 to 3.65 eV has been achieved on NiGeY/SiO₂ stacks. It was also found that the chemical potential of the material that is adjacent to the gate electrode/gate insulator plays an important role in the determination of the effective workfunction. This work-function tuning window was observed to decrease to a range of 5.08-4.25 eV on NiGeY/HfO₂ stacks.     

Improved short-channel FET performance with virtual extensions

Here, for the first time, a method is presented to use electrostatic coupling from a metal of appropriate workfunction, separated from the extension region by a thin insulator, to create an electrostatically-induced charge layer in doped source/drain CMOS. This "virtual extension" allows for lower extension doping and increased underlap between the doped extension and the gate, "sharpening" the carrier profile and improving short-channel device performance. In one example, clock-limiting n-FET switching currents are improved 25% using this approach. However, the improvement in switching speed due to this higher current is partially offset by capacitance between the metal overlap and the extension.     

硅缓冲层提高选区外延生长硅基锗薄膜质量

研究了Si缓冲层对选区外延Si基Ge薄膜的晶体质量的影响。利用超高真空化学气相沉积系统,结合低温Ge缓冲层和选区外延技术,通过插入Si缓冲层,在Si/SiO_2图形衬底上选择性外延生长Ge薄膜。采用X射线衍射(XRD)、扫描电子显微镜(SEM)、原子力显微镜(AFM)表征了Ge薄膜的晶体质量和表面形貌。测试结果表明,选区外延Ge薄膜的晶体质量比无图形衬底外延得到薄膜的晶体质量要高;选区外延Ge薄膜前插入Si缓冲层得到Ge薄膜具有较低的XRD曲线半高宽以及表面粗糙度,位错密度低至5.9×10~5/cm^2,且薄膜经过高低温循环退火后,XRD曲线半高宽和位错密度进一步降低。通过插入Si缓冲层可提高选区外延Si基Ge薄膜的晶体质量,该技术有望应用于Si基光电集成。     

Post metallization annealing study in La2O3/Ge MOS structure

The study on post metallization annealing (PMA) in electrical characteristics and interfacial properties of La₂O₃/Ge structures has been conducted. The PMA treatment in N₂ ambient induces the growth of interfacial Ge oxide layer accompanied with decrease of capacitance value and interface trap density. The interface-layer growth is caused by the oxidation of Ge substrate due to the hydroxyl group absorbed in La₂O₃ from the ambient. The metal electrode capping might prevent the hydroxyl from evaporating during annealing, which enhances the interface reaction. On the other hand, leakage current increment has been observed for the sample with PMA in case of using Pt gate electrode. It is due to the diffusion of Pt and/or Ge and a Pt-germanide formation in La₂O₃ film during PMA. This leakage current increment can be suppressed by using Ta or W electrode which has less reactivity with Ge than Pt at high temperature.     

Transition from the two- to three-dimensional growth of Ge films upon deposition onto relaxed SiGe/Si(001) buffer layers

The critical thickness of the two-dimensional growth of Ge on relaxed SiGe/Si(001) buffer layers different in Ge content is studied in relation to the parameters of the layers. It is shown that the critical thickness of the two-dimensional growth of Ge on SiGe buffer layers depends on the lattice mismatch between the film and the substrate and, in addition, is heavily influenced by Ge segregation during SiGe-layer growth and by variations in the growth-surface roughness upon the deposition of strained (stretched) Si layers. It is found that the critical thickness of the two-dimensional growth of Ge directly onto SiGe buffer layers with a Ge content of x = 11–36% is smaller than that in the case of deposition onto a Si (001) substrate. The experimentally detected increase in the critical thickness of the two-dimensional growth of Ge with increasing thickness of the strained (stretched) Si layer predeposited onto the buffer layer is attributed to a decrease in the growth-surface roughness and in the amount of Ge located on the surface as a result of segregation.     

铁氧体驱动与双路功率MOS单片集成电路研究

介绍了一种集成低压铁氧体驱动器和功率MOS管的单片集成电路。其内建驱动器工作电压9 V,功率MOS管极限电压大于80 V,工作电流3 A。该电路内含D/A转换器、双路比较器、触发器和组合逻辑电路,以及过频过压保护等功能,采用键合SOI深槽的CMOS/LDMOS工艺制作。     

Pure germanium epitaxial growth on thin strained silicon-germanium graded layers on bulk silicon substrate for high-mobility channel metal-oxide-semiconductor field-effect transistors

We demonstrate epitaxially grown high-quality pure germanium (Ge) on bulk silicon (Si) substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD) without involving growth of thick relaxed SiGe buffer layers. The Ge layer is grown on thin compressively strained SiGe layers with rapidly varying Ge mole fraction on Si substrates resulting in several SiGe interfaces between the Si substrate and the pure Ge layer at the surface. The presence of such interfaces between the Si substrate and the Ge layer results in blocking threading dislocation defects, leading to a defect-free pure Ge epitaxial layer on the top. Results from various material characterization techniques on these grown films are shown. In addition, capacitance-voltage (CV) measurements of metal-oxide-semiconductor (MOS) capacitors fabricated on this structure are also presented, showing that the grown structure is ideal for high-mobility metal-oxide-semiconductor field-effect transistor applications.