Validity of constant voltage stress based reliability assessment of high-/spl kappa/ devices

Charge trapping in high-/spl kappa/ gate dielectrics affects the result of electrical characterization significantly. DC mobility degradation and device threshold voltage instability and C-V and I-V hysteresis are a few examples. The charging effects in high-/spl kappa/ gate dielectric also affect the validity of conventional reliability test methodologies developed for SiO/sub 2/ devices. In this paper, we review high-/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl kappa/ devices.     

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Special reliability features for Hf-based high-/spl kappa/ gate dielectrics

Several special reliability features for Hf-based high-/spl kappa/ gate dielectrics are highlighted, including: 1) trapping-induced threshold voltage (V/sub th/) shift is much more of a concern than TDDB in determining the operating lifetime; 2) n-channel MOSFETs (nMOSFETs) are more vulnerable than p-channel MOSFETs (pMOSFETs); and 3) MOSFETs with polySi gates are more vulnerable than those with metal gates. These will be discussed in the context of existing electron/hole traps and trap generation by high-field stress. A novel technique to probe traps in ultrathin gate dielectrics, inelastic electron tunneling spectroscopy (IETS), will be shown to be capable of revealing the energies and locations of traps in high-/spl kappa/ gate dielectrics.     

Simulations of Sub-100 nm Strained Si MOSFETs with High-κ Gate Stacks

By including soft-optical phonon scattering within an ensemble Monte Carlo simulator, this paper studies the impact of high-κ gate stacks on the performance of n-type Si and strained Si MOSFETs. The simulated devices replicate the performance of sub-100 nm Si and strained Si MOSFETs fabricated by IBM. The results indicate a significant reduction in the device performance due to the presence of a high-κ gate dielectric in both Si and strained Si transistors.     

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.     

Enhanced SiO/sub 2/ reliability on deuterium-implanted silicon

Stress-induced leakage current and time-dependent dielectric breakdown were investigated to examine the reliability of gate oxides grown on hydrogen- and deuterium-implanted silicon substrates. An order of magnitude improvement in charge-to-breakdown was observed for the deuterium-implanted devices as compared with the hydrogen-implanted ones. Such reliability improvement may be explained by the reduction of defects in the SiO/sub 2/ and Si/SiO/sub 2/ interface, such as Si dangling bonds, weak Si-Si bonds, and strained Si-O bonds due to the retention of implanted deuterium at the interface and in the bulk oxide as confirmed by secondary ion mass spectroscopy.     

Dielectric-breakdown-induced epitaxy: a universal breakdown defect in ultrathin gate dielectrics

The breakdown phenomena in SiO/sub x/N/sub y/ (EOT=20 /spl Aring/) gate dielectric under a two- stage constant voltage stress in inversion mode are physically analyzed with the aid of transmission electron microscopy. The results show that dielectric-breakdown-induced epitaxy (DBIE) remains as one of the major failure defects responsible for gate dielectric breakdown evolution even for a stress voltage as low as 2.5 V. Based on the results, the same failure mechanism i.e., presence of DBIE would be responsible for the degradation in ultrathin gate dielectrics for gate voltage below 2.5 V. It is believed that DBIE will be present in MOSFETs failed at nominal operating voltage.     

SEU reliability analysis of advanced deep-submicron transistors

A systematic evaluation of the single-event-upset (SEU) reliability of the advanced technologies-high-/spl kappa/ gate dielectric, elevated source-drain (E-SD), and lateral asymmetric channel (LAC) MOSFETs is presented for the first time in this work. Our simulations results gives a clear view of how the short channel effects in a device governs its SEU reliability and how this reasoning evolves at the circuit level. It is shown that devices with worsened short-channel effects (high-/spl kappa/ gate dielectric transistors) have a significantly reduced SEU-reliability in contrast to the devices with controlled short-channel effects (LAC and E-SD) or even a conventional device.     

Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress

Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO/sub 2//HfO/sub 2//TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO/sub 2/ layer (IL) or high-/spl kappa/ layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO/sub 2/ layer. The generated traps can be passivated by a forming gas or nitrogen (N/sub 2/) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-/spl kappa/ stacks.     

Simulation Study of High Performance III-V MOSFETs for Digital Applications

We have studied the performance potential of an 80 nm physical gate length MOSFET with GaAs channel and high-k gate insulator using ensemble Monte Carlo simulations. The results show that a such device could deliver a 100–125% increase in the drive current compared to conventional MOSFETs with analogous channel lengths and device structure. This improvement is much higher than the 20–30% drive current increase in similar devices with strained Si channels on virtual SiGe substrates.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

Magnetic resonance studies of trapping centers in high-/spl kappa/ dielectric films on silicon

The electrical properties of high dielectric constant materials being considered for replacements of SiO/sub 2/ in metal-oxide semiconductor (MOS) field effect transistors are dominated by point defects. These point defects play important roles in determining the response of these films in almost any imaginable reliability problem. A fundamental understanding of these defects may help to alleviate the problems which they can cause. The best known methods for determining the structure of electrically active defects in MOS materials and devices are conventional electron spin resonance (ESR) and electrically detected magnetic resonance (EDMR). In this paper, we review the limited ESR and EDMR work performed to date on high-/spl kappa/ materials. A discussion of magnetic resonance techniques as well as a brief overview of the extensively studied Si/SiO/sub 2/ system is also included.     

Hot carrier degradation of HfSiON gate dielectrics with TiN electrode

Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-/spl kappa/ gate stack devices are severe than the one in the SiO/sub 2//poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.     

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.     

Conduction band-edge States associated with the removal of d-state degeneracies by the Jahn-Teller effect

X-ray absorption spectroscopy (XAS) is used to study band edge electronic structure of high-/spl kappa/ transition metal (TM) and trivalent lanthanide rare earth (RE) oxide gate dielectrics. The lowest conduction band d/sup */-states in TiO/sub 2/, ZrO/sub 2/ and HfO/sub 2/ are correlated with: 1) features in the O K/sub 1/ edge, and 2) transitions from occupied Ti 2p, Zr 3p and Hf 4p states to empty Ti 3d-, Zr 4d-, and Hf 5d-states, respectively. The relative energies of d-state features indicate that the respective optical bandgaps, E/sub opt/ (or equivalently, E/sub g/), and conduction band offset energy with respect to Si, E/sub B/, scale monotonically with the d-state energies of the TM/RE atoms. The multiplicity of d-state features in the Ti L/sub 2,3/ spectrum of TiO/sub 2/, and in the derivative of the O K/sub 1/ spectra for ZrO/sub 2/ and HfO/sub 2/ indicate a removal of d-state degeneracies that results from a static Jahn-Teller effect in these nanocrystalline thin film oxides. Similar removals of d-state degeneracies are demonstrated for complex TM/RE oxides including Zr and Hf titanates, and La, Gd and Dy scandates. Analysis of XAS and band edge spectra indicate an additional band edge state that is assigned Jahn-Teller distortions at internal grain boundaries. These band edges defect states are electronically active in photoconductivity (PC), internal photoemission (IPE), and act as bulk traps in metal oxide semiconductor (MOS) devices, contributing to asymmetries in tunneling and Frenkel-Poole transport that have important consequences for performance and reliability in advanced Si devices.     

Hot-Carrier- and Constant-Voltage-Stress-Induced Low-Frequency Noise in Nitrided High- $k$ Dielectric MOSFETs

Understanding and minimization of low-frequency noise (LFN) originating from high- $k$ (HK) gate dielectrics in newgeneration MOSFETs are of critical importance to applications in RF, analog, and digital circuits. To understand the effect of stress conditions on noise, nMOSFETs were subjected to accelerated hot-carrier stress (HCS) and positive constant-voltage stress (CVS). The additional LFN introduced through stressing was evaluated on nMOSFETs with TiN metal gate and HfSiON gate dielectric. Nitridation of HfSiO gate-dielectric MOSFETs was achieved by either a high-temperature $hbox{NH}_{3}$ anneal or a lower temperature plasma anneal. Influence of different dielectric nitridation procedures on the stress-induced degradation of transconductance, threshold properties, and LFN was studied. Worst degradation conditions, i.e., $V_{g} = V_{d}$, were used for HCS, whereas for CVS, the vertical field was fixed at 10 MV/cm for all transistors to achieve comparable stressing conditions. Plasma-nitrided devices showed less increase in their noise in the linear operation region than the thermally nitrided devices. This difference in noise behavior is attributed to the nitrogen profile across the HK/Si interface and in the bulk of the HK oxide caused by different nitridation techniques. The dielectric defect profile resultant from different annealing techniques was consistent with the spectral form of the observed drain-voltage LFN.      

Intrinsic reliability projections for a thin JVD silicon nitridegate dielectric in P-MOSFET

A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si₃N₄ gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As a result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to project the drift of a MOSFET incorporating JVD nitride at a low operating voltage of 1.2 V in 10 years. Based on these projections, we conclude that the increase in the Si₃N₄ gate dielectric leakage current does not pose a serious threat to device performance. Instead, the degradation in the threshold voltage and channel mobility can become the factor limiting the device reliability     

Simulations of Scaled Sub-100 nm Strained Si/SiGe p-Channel MOSFETs

This paper investigates scaled sub-100 nm strained Si channel p-type MOSFETs. For a 30–40% Ge content SiGe buffer, 1D Poisson-Schrödinger analysis indicates that the parasitic effects of the SiGe buffer are negligible in small devices with high n-type channel doping (>10¹⁷ cm^?3). The device published by IBM and calibrated by us has been scaled down to a 35 nm physical gate length and shows notable performance enhancement over the Si control MOSFET. Well-tempered MOSFET designs have also been adopted to study potential performance improvement associated with the introduction of a strained Si channel. These provide a performance improvement comparable with the scaled versions of the IBM devices for effective gate length down to 25 nm. Improved well engineering is required to suppress short channel effects during the scaling process.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Impact of phonon scattering in Si/GaAs/InGaAs nanowires and FinFets: a NEGF perspective

This paper reviews our previous theoretical studies and gives further insight into phonon scattering in 3D small nanotransistors using non-equilibrium Green function methodology. The focus is on very small gate-all-around nanowires with Si, GaAs or InGaAs cores. We have calculated phonon-limited mobility and transfer characteristics for a variety of cross-sections at low and high drain bias. The nanowire cross-sectional area is shown to have a significant impact on the phonon-limited mobility and on the current reduction. In a study of narrow Si nanowires we have examined the spatially resolved power dissipation and the validity of Joule’s law. Our results show that only a fraction of the power is dissipated inside the drain region even for a relatively large simulated length extension (approximately 30 nm). When considering large source regions in the simulation domain, at low gate bias, a slight cooling of the source is observed. We have also studied the impact of the real part of phonon scattering self-energy on a narrow nanowire transistor. This real part is usually neglected in nanotransistor simulation, whereas we compute its impact on current–voltage characteristic and mobility. At low gate bias, the imaginary part strongly underestimated the current and the mobility by 50 %. At high gate bias, the two mobilities are similar and the effect on the current is negligible.