Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

An As-P double-diffused lightly doped drain (LDD) device has been designed and fabricated with a self-aligned titanium disilicide process. The device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current. Threshold voltage and subthreshold characteristics of this device do not deviate from those of a conventional device without LDD and silicide. The drain avalanche breakdown voltage of the LDD device is higher by 2.5 V over the conventional device. Transconductance degradation was observed for the LDD devices due to the inherently high source-drain series resistance of the LDD structure. Substrate current is reduced and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain diffusion and the polysilicon gate to 3 Ω/sq compared with 150 Ω/sq of the unsilicided counterparts. It is also found that larger polysilicon grain size increases the sheet resistance of the silicide gate due to discontinuous titanium disilicide formation on top of polysilicon.     

非对称轻掺杂漏(LDD)MOSFET

提出并制作了一种仅有漏端轻掺杂区的MOSFET新结构──非对称LDD MOSFET。它与通常LDD MOSFET相比,抑制热载流子效应的能力相同,源漏串联电阻降低40％左右,线性区和饱和区的跨导分别增加50％和20％左右。用该器件制作的CMOS电路,其速度性能优于通常LDD MOSFET制作的同样电路。     

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.     

A MOS Transistor with self-aligned polysilicon source—drain

A new MOS transistor with self-aligned polysilicon source-drain (SAPSD) is demonstrated. Using a thin implant-doped polysilicon layer above the active channel region, a shallow source-drain junction with negligible leakage is realized. A novel lightly doped-drain (LDD) structure is also incorporated by diffusing dopants from the n+ polysilicon source-drain layer into the silicon substrate, forming the n- region. During the gate oxidation, a sidewall spacer is simultaneously formed by the oxidation of polysilicon source-drain sidewalls. The transistor layout area is saved by bringing the source-drain contacts onto the field oxide region. Experimental results of the new structure are presented.     

Use of sacrificial spacers for fabricating LDD transistors in a CMOS process

The use of sacrificial spacers for LDD transistors in a CMOS process is described. LPCVD nitride or PSG is employed as the sidewall-spacer material which is selectively etched off after the LDD's n-/n+ junction formation, thus allowing subsequent shallow p+ implant self-aligning to the polysilicon gate. Deeper n-/n+ junctions with adequate drain/gate overlap for n-channel LDD transistors to minimise hot-electron effects can then be made while simultaneously the shallow p+ junction with high punch-through immunity is preserved for p-channel transistors. The conflicting diffusion requirements in forming n-/n+ and p+ source-drain junction depths are therefore decoupled.     

Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

The LDD structure, where narrow, self-aligned n/sup -/ regions are introduced between the channel and the n/sup +/ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of then- dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n- regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 /spl mu/m. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 X basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.     

Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology

This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED.     

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.     

LDD design tradeoffs for single transistor latch-up and hot carrierdegradation control in accumulation mode FD SOI MOSFET's

An experimental study has been conducted of the design tradeoffs of fully-depleted (FD) accumulation mode Silicon-on-Insulator (SOI) MOSFET's with regard to hot carrier reliability, single transistor latch-up and device performance. Three drain designs were considered, using Large-Tilt-Angle Implantation (LATID) for the LDD formation. Structures incorporating 0° angle LDD implant, large angle LDD implant, and no LDD were fabricated, and their hot carrier reliability, single transistor latch-up voltage, and device performance in terms of drive current and speed were determined. Correct interpretation of the experimental results was aided by performing PISCES numerical simulations. It was found that the structure with the best hot carrier reliability (large angle LDD implant) has the worst case latch-up voltage, and the one with the worst hot carrier reliability (no LDD implant) has the best latch-up voltage. Overall good device performance with acceptable hot carrier reliability and latch-up voltage is obtained with the 0° angle LDD implant     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

Implementation of fully self-aligned bottom-gate MOS transistor

This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 /spl mu/m are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm/sup 2//V-s, off-current of 0.17 pA//spl mu/m, and on-off current ratio of 7.1/spl times/10/sup 8/.     

A new half-micrometer p-channel MOSFET with efficient punchthrough stops

This paper describes design and characteristics of a new half-micrometer buried p-channel MOSFET with efficient punch-through stops. The approach for scaling down the buried p-channel MOSFET's is discussed by using two-dimensional process/device simulations and experimental results. The efficient punchthrough stops have realized high punchthrough resistance in half-micrometer dimensions without increasing the n-well concentration and extreme scaling of channel and source-drain junction depths. Moreover, this p-channel MOSFET shows the breakdown voltage to be as high as 10 V. The fabrication sequence is compatible with the conventional n-channel LDD MOSFET's.     

A novel laser-processed self-aligned gate-overlapped LDD poly-SiTFT

A novel process for fabricating self-aligned gate-overlapped LDD (SAGOLDD) poly-Si thin film transistors (TFTs) was demonstrated. Laser irradiation for dopant activation was performed from the backside of the quartz wafer. The graded LDD structure was naturally formed under the gate edges due to the lateral diffusion of the dopants during the laser activation. In comparison with the conventional laser-processed self-aligned poly-Si TFTs, the SAGOLDD poly-Si TFTs exhibited lower leakage current, suppressed kink effect, and higher reliability. Moreover, the proposed process was simple and very suitable for low-temperature processing     

MOSFET drain engineering analysis for deep-submicrometerdimensions: a new structural approach

A new MOS transistor structural approach (hot-carrier-induced MOSFET) capable of substantially suppressing adverse hot-carrier effects, while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFETs (L _gate⩽0.35 μm) is described. This structure is unique in having a lower doped N^- region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFETs have an N^- region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions     

Performance and reliability evaluation of high dielectric LDDspacer on deep sub-micrometer LDD MOSFET

High dielectric LDD spacer has been proposed to achieve both reliability and performance improvement on the scaled LDD MOSFET's. However, the sidewall polyoxide and spacer bottom oxide required for process reliability issue will adversely limit the DC performance improvement gained by using high dielectric LDD spacer. AC performance is evaluated by the transconductance cutoff frequency determined by the transconductance, G_M and total gate capacitance, C_GG . For deep-submicron MOSFET's, the dominance of gate to source/drain overlap capacitance in C_GG has significant impact on the AC performance. The increase of C_GG due to the enhanced fringe field from high dielectric LDD spacer significantly dominates over the increase of transconductance, and then deteriorates the AC performance. As the reliability issue is concerned, the key doping profile, N^- source/drain lateral diffusion profile was obtained from the two dimensional process simulator SUPREM-IV corresponding to wide range of LDD N^- doses. The optimized N ^- dose designed for hot carrier reliability issue (under V _GS-V_T=0.5 V_DS operation) is located around 2×10¹³ cm^-2 for both conventional LDD (denoted as OLDD in this paper) and high dielectric LDD (HLDD) devices. However, the improvement achieved by using HLDD instead of OLDD devices is then turned out to be insignificant under this optimized N^- dose condition     

The impact of N-drain length and gate—drain/source overlap on submicrometer LDD devices for VLSI

To obtain optimal values for the key factors in enchancing the reliability and performance of deep submicrometer lightly doped drain (LDD) structures, the influence of LDD device parameters-n-drain length Ln, gate-drain/source overlap length Γ, and n- dose Nd-on reliability and performance were investigated using a three-dimensional (3-D) device simulator and experiment. A new device structure is discussed as a guide for deep submicrometer LDD design. This structure makes an advantageous use of the gate-drain overlap effect without scaling of Lnand Γ.     

A new LDD structure: total overlap with polysilicon spacer (TOPS)

The total overlap with polysilicon spacer (TOPS) structure, a fully overlapped lightly doped drain (LDD) structure, is discussed. The TOPS structure achieves full gate overlap of the lightly doped region with simple processing. TOPS devices have demonstrated superior performance and reliability compared to oxide-spacer LDD devices, with an order of magnitude advantage in current degradation under stress for the same initial current drive or 30% more drive for the same amount of degradation. TOPS devices also show a much smaller sensitivity to n^- dose variation than LDD devices. Gate-induced drain leakage is reported for the first time in fully overlapped LDD devices     

Performance and reliability aspects of FOND: a new deep submicronCMOS device concept

The electrical performance and the hot-carrier degradation behavior of a new type of fully overlapped device called FOND (Fully Overlapped Nitride-etch defined Device) is analyzed and compared to that of conventional LDD devices. Similar current driveability is found for the FOND devices compared to conventional LDD devices although in the FOND device significantly smaller concentrations are used for the lightly doped n^--regions. For the overlapped device, a higher gate and overlap capacitance is found, originating from a larger poly length and self-alignment of the junction implant to the poly. For identical voltage conditions, this is reflected in a somewhat lower ring oscillator speed, compared to the LDD case. Concerning reliability, it is shown that deep submicron FOND devices can easily exceed the lifetime of the conventional LDD devices by two orders of magnitude. Based on experimental and simulation results, this higher hot-carrier resistance is explained by a smaller hot-carrier generation and a lower sensitivity of the overlapped device to hot-carrier damage. For the nMOS transistors, the lower generation of damage is the result of the lower lateral electric field due to the low n^- concentration and the overlap of the polysilicon gate on the n^- region while the suppressed sensitivity is due to the complete overlap. Compared to LDD devices, the use of fully overlapped devices creates a wider process and reliability margin that can be used to optimize other electrical parameters     

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

The LDD structure, where narrow, self-aligned n^-regions are introduced between the channel and the n⁺source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n^-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n^-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.     

Suppression of hot-carrier effects in submicrometer CMOS technology

Approaches used to suppress the hot-carrier effects in submicrometer CMOS technology based on the drain engineering of the device structure and process-induced deice degradation are discussed. Different types of lightly doped drain (LDD) structures are studied. Several process-related device aging issues are discussed. Twin-Tub V CMOS technology is used as an example of how to manage the hot-carrier issues with respect to the process integration aspects