Highly Linear Coherent Receiver With Feedback

We propose and demonstrate a novel coherent receiver with feedback for high-linearity analog photonic links. In the proposed feedback receiver, a local phase modulator tracks the phase change of the signal and reduces the effective swing across the phase demodulator without reducing the transmitted signal. The signal-to-noise-ratio is thus maintained while linearity is improved. Up to 20-dB improvement in spur-free dynamic range (SFDR) is achieved experimentally. At 3.13 mA of average photocurrent per photodiode, the measured SFDR is 124.3 dBmiddotHz^2/3, which corresponds to an SFDR of 131.5 dBmiddotHz^2/3 when the link is shot-noise-limited     

A Blocker Filtering Technique for SAW-Less Wireless Receivers

An active filtering technique to remove the out-of-band blockers in wireless receivers is presented. The circuit employs a feed-forward filtering path to produce an arbitrarily narrow frequency response in the low-noise amplifier (LNA), eliminating the need for an external surface acoustic wave (SAW) filter at the receiver front-end. The required notch filtering in the feed-forward path is realized through a receiver translational loop, driven by the same local oscillator (LO) signals used in the main receiver. For the proof of concept, a prototype amplifier in 65 nm standard CMOS, intended for Global System for Mobile Communication (GSM) applications, is implemented. When the filtering is enabled, the amplifier 3-dB bandwidth reduces from 220 MHz to about 4.5 MHz, and a stop-band rejection of over 21 dB is achieved.     

一种适用于低中频和零中频GPS接收机的CMOS混频器

基于0.18 μm RF CMOS工艺,设计了一种可用于低中频和零中频GPS接收机的CMOS正交混频器.通过固定电流注入技术,减小了混频器的噪声系数.将混频器的开关管偏置在线性区,可进一步降低混频器的1/f噪声,适用于零中频接收机.在1.8 V的工作电压下,由Cadence Spectre RF仿真可得,混频器的转换增益为7.1 dB,而4 MHz和20 kHz中频输出的SSB噪声系数分别为8.7 dB和12.3 dB.     

多双曲正切法则在高线性度CMOS混频器设计中的分析与应用

研究了CMOS电路中多双曲正切法则的应用对线性度产生的影响.分析并推导了两种非平衡差分对结构的差分输出电流和等效跨导的公式.给出了电路线性度最优时,多补偿偏置结构的补偿偏置电压VK的表达式.基于理论分析结果,设计了一个应用多双曲正切法则的CMOS吉尔伯特混频器电路.流片采用UMC 0.18 μm RF-CMOS工艺,经过测量,所得到的参数与理论分析及仿真值吻合,证明了理论分析的可行性.     

一个应用于探测生理信号SoC中的CMOS全集成高线性度低噪声上变频器设计

本文设计一款用于探测生理信号SoC芯片中的5GHz双边带上变频器.该混频器基于传统的吉尔伯特单元,采用交流耦合current-bleeding结构以及三阶非线性失真抵消技术抑制非线性.通过将跨导级晶体管偏置在不同的工作区域(transconductance-boost结构),使得带内变频损失小于5dB而IIP3介于22.3dBm到39.8dBm,而且双边带噪声指数小于8.2dB.应用全差分结构和感性源极钝化,再次抑制了二阶以及三阶失真.全部上变频器在1.2V供电条件下总功耗为8.4mW.     

一种高线性宽带CMOS全差分放大器

设计了一种高线性度的宽带CMOS全差分放大器,输入级采用带有电阻共模负反馈的差分电路,输出级则由推挽跨导运算放大器及其反馈环路组成.采用输入级源退化电阻及输出级负反馈技术,使得差分输出峰峰值为1 V时三阶谐波失真达到-60 dB.同时利用反馈环路中反馈电容的欠阻尼滞后补偿作用,使放大器的带宽增大了15%.测试结果表明,在0.25 μmCMOS工艺下,该放大器-3 dB带宽达到150 MHz,噪声系数小于14 dB.     

一种应用于GPS射频前端的低噪声混频器

为了克服混频器噪声对GPS接收机灵敏度造成的影响,设计了一种应用于GPS射频前端的低噪声混频器电路.采用自偏置缓冲级放大本振信号,有效地提高了电路性能.该混频器的转换增益为23 dB,噪声系数为4.55 dB,3阶交调点为-9.36 dBm,在1.57 GHz到1.6 GHz频段上,反射系数S11小于-15 dB,电路采用1.8 V电压供电;混频器核心电路静态工作电流1.2 mA,采用CMOS 0.18 μm工艺实现,芯片版图面积为160μm×360μm.     

Tunable Highly Linear Floating-Gate CMOS Resistor Using Common-Mode Linearization Technique

In this paper, an implementation of a tunable highly linear floating resistor that can be fully integrated in CMOS technology is presented. The second-order effects of a single MOS transistor operating in the triode operation regime are described, and a common-mode linearization technique is applied to suppress these nonlinearities. This technique is implemented by utilizing a low-power circuit design strategy that exploits the capacitive coupling and the charge storage properties of floating-gate transistors. The resistance of the proposed circuit is tuned by utilizing the Fowler-Nordheim tunneling and hot-electron injection quantum-mechanical phenomena. We demonstrate the use of this resistor in highly linear amplifier. We present experimental data from the chips that were fabricated in a 0.5- CMOS process. We show that this resistor exhibits 0.024% total harmonic distortion (THD) for a sine wave with amplitude. Also, we show the programmability of the amplifier gain using the proposed tunable resistor.     

用于数字电视调谐芯片的高线性CMOS VGA

设计了一种适于DVB-C标准的中频可变增益放大器。该放大器由三部分构成:电流调节型可变增益单元、基于差分对管传输特性的指数控制电压产生电路以及一高线性输出级。采用Chartered0.25μm RFCMOS工艺库下流片。测试结果表明,4～49dB的连续增益范围,100MHz的3dB带宽,50Ω负载下的OIP3为16.8dBm。     

A Highly Linear CMOS Baseband Chain for Wideband Wireless Applications

The emergence of wide channel bandwidth wireless standards requires the use of a highly linear, wideband integrated CMOS baseband chain with moderate power consumption. In this paper, we present the design of highly linear, wideband active RC filters and a digitally programmable variable gain amplifier. To achieve a high unity gain bandwidth product with moderate power consumption, the feed‐forward compensation technique is applied for the design of wideband active RC filters. Measured results from a 0.5 µm CMOS prototype baseband chain show a cutoff frequency of 10 MHz, a variable gain range of 33 dB, an in‐band IIP3 of 13 dBV, and an input referred noise of 114 µVrms while dissipating 20 mW from a 3 V supply.     

一种高线性度CMOS栅压自举采样开关

分析了影响MOS采样开关性能的非理想因素,提出了一种新型的栅压自举采样开关,该结构不仅能通过稳定开关管的栅源电压消除导通电阻变化带来的影响,而且能通过虚拟管来消除电荷注入带来的影响。基于华润上华0.13 um标准数模混合工艺,采用Cadence软件对电路进行了模拟,模拟结果显示这种开关线性度高,适合应用于高速高精度模数转换器中。     

A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer

A low-power frequency tripler is designed by using the sub-harmonic mixer configuration for K-band applications. The proposed circuit features quadrature signal generation, applicable to LO signal synthesis in millimeter-wave wireless transceivers. It achieves conversion gain of $-$5.7 dB at the output frequency of 21 GHz. Implemented in a 0.18 $mu{rm m}$ CMOS technology, the circuit consumes power of 7.5 mW with 1.5 V supply voltage. The entire die occupies an area of $1000times 1050 mu{rm m}^{2}$.      

A Highly Linear Wideband Up-Conversion Differential CMOS Micromixer Using IMD3 Cancellation for a Digital TV Tuner IC

In this letter, a highly linear wideband up-conversion differential CMOS micromixer with a linearized transconductor employing a third order intermodulation (IMD3) cancellation technique for a digital TV tuner IC is proposed and designed. It is fabricated in a 0.18 $mu$ m CMOS process and draws 22 mA from a 1.8 V supply voltage. It shows a voltage gain of more than 6 dB, a noise figure lower than 11.9 dB, an IIP2 of more than 57 dBm, and an IIP3 of more than 18 dBm for the entire input band from 48 to 860 MHz.      

Design of a Low Voltage Highly Linear 2.4 GHz Up-Conversion Mixer in 0.18 μm CMOS Technology

This paper presents a low voltage highly linear up-conversion mixer for 2.4 GHz IEEE 802.11b WLAN transmitter applications based on a Chartered 0.18 μm CMOS technology. In the proposed mixer, the double balanced Gilbert cell topology was adopted and the dual resistive current-reuse and current-bleeding techniques in both the driver and switching stages with a capacitive cross-coupling technique were used. The up-conversion mixer can convert a 10 MHz intermediate frequency signal to a 2.4 GHz radio frequency signal, with a local oscillator power of 0 dBm at 2.39 GHz. A comparison with conventional CMOS mixer shows that this up-conversion mixer has advantages of low voltage, low power consumption and high performance. The post-layout simulation results demonstrate that at 2.4 GHz, the circuit provides 7.1 dB of conversion gain and the input-referred third-order intercept point of 11.3 dBm, while drawing only 5 mA for the mixer core under a supply voltage of 1.2 V. The chip area including testing pads is only 0.65 × 0.75 mm.     

A New Linearization Technique for CMOS RF Mixer Using Third-Order Transconductance Cancellation

A new third-order transconductance (g_m3) cancellation technique is proposed and applied to a conventional radio frequency (RF) mixer for improving circuit linearity. The bulk-to- source voltage is applied to adjust the peak value position of gms. The cancellation of g_m3 is utilized by a negative peak g_m3 transistor combined in parallel with a positive peak g_m3 transistor. For a single device, the measured adjacent channel power ratio (ACPR) and third-order intermodulation (IMD3) distortion are both improved over 15 dB. A Gilbert-cell mixer in commercial 0.18-mum CMOS process was designed using the proposed method to further evaluate the linearity. The compensated g_m3 device is placed in the input RF gm-stage and then reducing the principle nonlinearity source of the mixer. From the experiment results, the ACPR and IMD3 of the mixer are improved about 10 and 15 dB, respectively.     

A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider

A heterodyne receiver performs frequency down-conversion in two steps to relax oscillator and divider speed requirements. The receiver incorporates new concepts such as a current-domain quadrature separation method, a broadband Miller divider based on a passive mixer, and an inductor nesting technique that significantly reduces the length of high-frequency interconnects. Fabricated in 90-nm CMOS technology, the circuit achieves a noise figure of 6.9 to 8.3 dB from 49 GHz to 53 GHz with a gain of 26 to 31.5 dB and I/Q mismatch of 1.6 dB/6.5deg.     

CMOS Micromachined Inductors With Structure Supports for RF Mixer Matching Networks

This letter presents the comparison of three novel structure supports for on-chip complementary metal–oxide–semiconductor (CMOS)-based micromachined inductors by using a proposed two-step maskless post-CMOS process. A 3-D electromagnetic inductor simulation model is established and calibrated with inductor fabrication. The proposed inductors are applied in the matching network of the double-balanced Gilbert mixer to improve the performance and the mechanical stability. The mixers, with and without micromachined process inductors, are fabricated in a 0.5-$muhbox{m}$ CMOS process and compared in this letter. The measurement results show a 28.12% increase in conversion gain, a 31.7% improvement in third intercept point, and a 44% reduction in the noise figure.      

A CMOS Harmonic Rejection Mixer With Mismatch Calibration Circuitry for Digital TV Tuner Applications

A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-$mu$m CMOS technology. Odd harmonic mixing in the 48–862 MHz digital TV frequency band between the input signal and the local oscillator harmonics is a critical problem for direct-conversion receivers which require a harmonic rejection of over ${-}{hbox {60}}$ dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of ${-}{hbox {30}}$ to ${-}{hbox {40}}$ dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than ${-}{hbox {70}}$ dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.      

A Multibeam SIS Mixer Module for a Focal Plane Array Receiver

The integration of many receiver units into a receiver array is a common method of improvement of imaging systems. This approach, well known in the mm band for Schottky mixer arrays, has not so far been developed for Superconductor - Insulator - Superconductor (SIS) junction mixers, which give the best sensitivity in the short mm wave range and in the submm range. We demonstrate for the first time a practical low noise multibeam receiver module using SIS mixer technology. The basis for the integration of several SIS mixers with a common local oscillator source is given by the saturation of the SIS receiver noise dependence upon local oscillator power. The module comprises three identical SIS mixers integrated with a common local oscillator, coupled through a three branch waveguide directional coupler. The multibeam module has been developed for a focal plane array receiver of the 30 meter radio telescope of the Institut de Radioastronomie Millimétrique (IRAM).     

A New RF CMOS Gilbert Mixer With Improved Noise Figure and Linearity

The noise figure of an RF CMOS mixer is strongly affected by flicker noise. The noise figure can be improved using pMOS switch circuits, which insert current at the on/off crossing instants of the local oscillator switch stage because the circuits reduce the flicker noise injection. When it is applied to a conventional Gilbert mixer, the injection efficiency and linearity are degraded by the nonlinear parasitic capacitances of the pMOS switch circuits and the leakage through the parasitic path. We propose the pMOS switch circuits with an inductor, which tunes out the parasitic components at 2f_o and closes out the leakage path. The mixer fabricated in 0.13-mum CMOS at 2.4-GHz center frequency has provided improved characteristics for linearity and noise figure.