Investigation of Program Saturation in Scaled Interpoly Dielectric Floating-Gate Memory Devices

This paper investigates the program saturation in aggressively scaled interpoly dielectric (IPD) floating-gate (FG) cells for nand application. To describe the program saturation in IPD stacks containing thick suboxides $(geq hbox{4} hbox{nm})$ , a simple model was developed, directly yielding the maximum reachable programmed threshold voltage level for a given FG cell geometry. The presented model agrees very well to program saturation measurements carried out on a 48 nm FG nand technology with an IPD composed of $hbox{SiO}_{2}$ and $ hbox{Al}_{2}hbox{O}_{3}$. By extending the considerations to an arbitrary IPD, this paper represents the first attempt to quantify the IPD current blocking ability required for future scaled FG memory cells.      

AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio

In this letter, we propose using an oxide-filled isolation structure followed by $hbox{N}_{2}/hbox{H}_{2}$ postgate annealing to reduce the leakage current in AlGaN/GaN HEMTs. An off-state drain leakage current that is smaller than $hbox{10}^{-9} hbox{A/mm}$ (minimum $hbox{5.1} times hbox{10}^{-10} hbox{A/mm}$) can be achieved, and a gate leakage current in the range of $hbox{7.8} times hbox{10}^{-10}$ to $hbox{9.2} times hbox{10}^{-11} hbox{A/mm}$ ($V_{rm GS}$ from $-$10 to 0 V and $V_{rm DS} = hbox{10} hbox{V}$) is obtained. The substantially reduced leakage current results in an excellent on/off current ratio that is up to $hbox{1.5} times hbox{10}^{8}$. An improved flicker noise characteristic is also observed in the oxide-filled devices compared with that in the traditional mesa-isolated GaN HEMTs.      

Logic Operation of HTS SFQ Logic Family

A high-$T_{c}$ superconducting (HTS) single-flux-quantum (SFQ) logic family including an and gate, an or gate, and an inverter was designed. The circuit parameters were optimized for a Josephson junction's critical current density, which may change due to a temperature change or insufficient run-to-run reproducibility of the fabrication process. New circuit design layout rules were implemented to improve $I_{c}$ uniformity. As a result, all circuits were successfully tested and show at least $pm$40% critical current density operational margins. An effect of the parasitic capacitance formed by a junction electrode and a ground plane on the operating margins of the and gate was investigated by numerical simulation. Test circuits were fabricated using $hbox{YBa}_{2} hbox{Cu}_{3}hbox{O}_{7 - delta}$ ramp-edge junction technology and were operated at temperatures higher than 30 K. Bias current margins were also measured, and they found to be close to the simulated ones.      

Low On-Resistance High-Breakdown Normally Off AlN/GaN/AlGaN DHFET on Si Substrate

Ultrathin-barrier normally off AlN/GaN/AlGaN double-heterostructure field-effect transistors using an in situ SiN cap layer have been fabricated on 100-mm Si substrates for the first time. The high 2DEG density in combination with an extremely thin barrier layer leads to enhancement-mode devices with state-of-the-art combination of specific on-resistance that is as low as 1.25 $hbox{m}Omegacdothbox{cm}^{2}$ and breakdown voltage of 580 V at ${V}_{rm GS} = hbox{0} hbox{V}$ . Despite the 2-$muhbox{m}$ gate length used, the transconductance peaks above 300 mS/mm. Furthermore, pulsed measurements show that the devices are dispersion free up to high drain voltage ${V}_{rm DS} = hbox{50} hbox{V}$. More than 200 devices have been characterized in order to confirm the reproducibility of the results.      

Graphene Nanoribbon Tunnel Transistors

A graphene nanoribbon (GNR) tunnel field-effect transistor (TFET) is proposed and modeled analytically. Ribbon widths between 3 and 10 nm are considered to effect energy bandgaps in the range of 0.46 to 0.14 eV. It is shown that a 5-nm ribbon width TFET can switch from on to off with only 0.1-V gate swing. The transistor achieves 800 $muhbox{A}/muhbox{m}$ on -state current and 26 $hbox{pA}/muhbox{m}$ off-state current, with an effective subthreshold swing of 0.19 mV/dec. Compared to a projected 2009 $n$MOSFET, the GNR TFET can provide 5$times$ higher speed, 20$ times$ lower dynamic power, and 280 000$times$ lower off-state power dissipation. The high performance of GNR TFETs results from their narrow bandgaps and their 1-D nature.      

A Sub-0.2$^{circ}/$ hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching

This paper describes a system architecture and CMOS implementation that leverages the inherently high mechanical quality factor (Q) of a MEMS gyroscope to improve performance. The proposed time domain scheme utilizes the often-ignored residual quadrature error in a gyroscope to achieve, and maintain, perfect mode-matching (i.e., $sim$0 Hz split between the high-Q drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS IC and control algorithm have been interfaced with a 60 $mu{hbox {m}}$ thick silicon mode-matched tuning fork gyroscope $({rm M}^{2}mathchar"707B {rm TFG})$ to implement an angular rate sensing microsystem with a bias drift of 0.16$^{circ}/{hbox{hr}}$. The proposed technique allows microsystem reconfigurability—the sensor can be operated in a conventional low-pass mode for larger bandwidth, or in matched mode for low-noise. The maximum achieved sensor Q is 36,000 and the bandwidth of the microsensor can be varied between 1 to 10 Hz by electronic control of the mechanical frequencies. The maximum scale factor of the gyroscope is 88 ${hbox{mV}}/^{circ}/{hbox{s}}$ . The 3$~$ V IC is fabricated in a standard 0.6 $ mu{hbox {m}}$ CMOS process and consumes 6 mW of power with a die area of 2.25 ${hbox {mm}}^{2}$.      

Cyclic Codes and Sequences From Generalized Coulter–Matthews Function

In this paper, we will study the exponential sum $sum_{xin {BBF}_q}chi(alpha x^{(p^k+1)/2}+beta x)$ that is related to the generalized Coulter–Matthews function $x^{(p^k+1)/2}$ with $k/{rm gcd}(m,k)$ odd. As applications, we obtain the following: the correlation distribution of a $p$-ary $m$-sequence and a decimated $m$-sequence of degree ${p^k+1 over 2}$;      

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 $mu hbox{m}$ exhibits a BV of 500 V and specific on-resistance $(R_{{rm on}, {rm sp}}!)$ of 96 $hbox{m}Omega cdot hbox{cm}^{2}$, yielding to a power figure of merit $(BV^{2}!!/ !R_{{rm on}, {rm sp}})$ of 2.6 $hbox{MW}/hbox{cm}^{2}$ . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.      

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is $>$ 55 dB over a 200 MHz bandwidth centered around 5.25 $~$GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, $-$79 dBm sensitivity, 5.6 dB SSB NF, $-$7$~$ dBm IIP3, $-$18 dB $S_{11}$ and a 1 mm $times$ 2 mm die area in 0.18$ mu{hbox {m}}$ CMOS.      

Bandgap-Engineered Ga-Rich GaZnO Thin Films for UV Transparent Electronics

Ga-rich GaZnO thin films were prepared by metal–organic chemical vapor deposition. The optical bandgap of GaZnO films can be engineered from 3.3 to 4.9 eV by varying the Ga content. The film is amorphortized and the resistivity increases with an increase of Ga content. The Ga-rich GaZnO alloy with lower resistivity is investigated as a UV transparent conductor, while the semi-insulating Ga-rich GaZnO film with high transparency at 280–900 nm is employed as the channel layer to fabricate deep UV transparent thin-film transistor. The transistor shows a typical n-channel field-effect characteristic with a current on/off ratio of $hbox{10}^{4}$–$ hbox{10}^{5}$, a threshold voltage of $sim$42 V, a saturated field-effect mobility of $sim!hbox{0.06} hbox{cm}^{2} cdot hbox{V}^{-1} cdot hbox{s}^{-1}$, and a subthreshold swing of $ sim!hbox{7.7} hbox{V} cdot hbox{decade}^{-1}$.      

Lattice-Mismatched $hbox{In}_{0.4}hbox{Ga}_{0.6} hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel n-MOSFETs

We report the first demonstration of a strained $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ channel n-MOSFET featuring in situ doped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ source/drain (S/D) regions. The in situ silicondoped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ S/D was formed by a recess etch and a selective epitaxy of $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ in the S/D by metal–organic chemical vapor deposition. A lattice mismatch of $sim$0.9% between $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and $hbox{In}_{0.4} hbox{Ga}_{0.6}hbox{As}$ S/D gives rise to lateral tensile strain and vertical compressive strain in the $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ channel region. In addition, the in situ Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.      

Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation

Performance degradation of n-MOSFETs with plasma-induced recess structure was investigated. The depth of Si recess $(d_{R})$ was estimated from the experiments by using Ar gas plasmas. We propose an analytical model by assuming that the damage layer was formed during an offset spacer etch. A linear relationship between threshold voltage shift $(Delta V_{rm th})$ and $d_{R}$ was found. Device simulations were also performed for n-MOSFETs with various $(d_{R})$. Both $vertDelta V_{rm th}vert$ and off-state leakage current increased with an increase in $d_{R}$ . The increase in $vertDelta V_{rm th}vert$ becomes larger for smaller gate length. The results from device simulations are consistent with the analytical model. These findings imply that the Si recess structure induced by plasma damage enhances $V_{rm th}$-variability in future devices.      

Universal Lossless Compression of Erased Symbols

A source ${mmb X}$ goes through an erasure channel whose output is ${mmb Z}$. The goal is to compress losslessly ${mmb X}$ when the compressor knows ${mmb X}$ and ${mmb Z}$ and the decompressor knows ${mmb Z}$. We propose a universal algorithm based on context-tree weighting (CTW), parameterized by a memory-length parameter $ell$. We show that if the erasure channel is stationary and memoryless, and ${mmb X}$ is stationary and ergodic, then the proposed algorithm achieves a compression rate of $H(X_0vert X_{-ell}^{-1}, Z^ell)$ bits per erasure.      

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

Multigate GaN RF Switches With Capacitively Coupled Contacts

We present the analysis and the performance characteristics of novel III-Nitride multigate (MG) radio-frequency (RF) switches fabricated over AlGaN/GaN heterostructures using capacitively coupled contacts $(hbox{C}^{3})$. $ hbox{C}^{3}$ device technology does not require contact annealing and, thus, allows for fully self-aligned processing of MG devices with tight electrode spacing. The combination of $hbox{C}^{3}$ electrodes with MG RF switch design results in devices with significantly lower OFF-state capacitance, higher isolation, and higher RF switching power as compared to conventional FET-based RF switches.      

High-Temperature High-Power Operation of GaInNAs Laser Diodes in the 1220–1240-nm Wavelength Range

We report on the high-temperature performance of high-power GaInNAs broad area laser diodes with different waveguide designs emitting in the 1220–1240-nm wavelength range. Large optical cavity laser structures enable a maximum continuous-wave output power of $>$8.9 W at ${T}=20 ^{circ}$C with emission at 1220 nm and are characterized by low internal losses of 0.5 cm$^{-1}$ compared to 2.9 cm$^{-1}$ for the conventional waveguide structures. High-power operation up to temperatures of 120 $^{circ}$C is observed with output powers of $>$4 W at ${T}=90 ^{circ}$C. This laser diode showed characteristic temperatures of ${T}_{0} =112$ K and ${T}_{1}=378$ K.      

A 3-D High-Frequency Array Based 16 Channel Photoacoustic Microscopy System for In Vivo Micro-Vascular Imaging

This paper discusses the design of a novel photoacoustic microscopy imaging system with promise for studying the structure of tissue microvasculature for applications in visualizing angiogenesis. A new 16 channel analog and digital high-frequency array based photoacoustic microscopy system (PAM) was developed using an Nd:YLF pumped tunable dye laser, a 30 MHz piezo composite linear array transducer, and a custom multichannel receiver electronics system. Using offline delay and sum beamforming and beamsteering, phantom images were obtained from a 6 $mu{hbox {m}}$ carbon fiber in water at a depth of 8 mm. The measured $-6~{rm dB}$ lateral and axial spatial resolution of the system was $100pm 5~mu{hbox {m}}$ and $45pm 5~mu{hbox {m}}$, respectively. The dynamic focusing capability of the system was demonstrated by imaging a composite carbon fiber matrix through a 12.5 mm imaging depth. Next, 2-D in vivo images were formed of vessels around 100 $mu{hbox {m}}$ in diameter in the human hand. Three-dimensional in vivo images were also formed of micro-vessels 3 mm below the surface of the skin in two Sprague Dawley rats.      

Improved Electrical Performance and Uniformity of MILC Poly-Si TFTs Manufactured Using Drive-In Nickel-Induced Lateral Crystallization

A new manufacturing method for polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using drive-in nickel-induced lateral crystallization (DILC) was proposed. In DILC, a $ hbox{F}^{+}$ implantation was used to drive Ni in the $alpha$ -Si layer. To reduce Ni contamination, the remained Ni film was then removed and subsequently annealed at 590 $^{circ}hbox{C}$. It was found that DILC TFTs exhibit high field-effect mobility, low threshold voltage, low subthreshold slope, high on-state current, lower trap-state density, smaller standard deviations, and low off-state leakage current compared with conventional Ni-metal-induced lateral crystallization TFTs.      

Microwave ZnO Thin-Film Transistors

We have developed ZnO thin-film transistor design and fabrication techniques to demonstrate microwave frequency operation with 2-$muhbox{m}$ gate length devices produced on GaAs substrates. Using $hbox{SiO}_{2}$ gate insulator and pulsed laser deposited ZnO active layers, a drain–current on/off ratio of $hbox{10}^{12}$, a drain–current density of 400 mA/mm, a field-effect mobility of $hbox{110} hbox{cm}^{2}!/ hbox{V}!cdothbox{s}$, and a subthreshold gate voltage swing of 109 mV/dec were achieved. Devices with Ti-gate metal had current and power gain cutoff frequencies of 500 and 400 MHz, respectively.      

High-Speed 2$, times ,$2 Switch for Multiwavelength Silicon-Photonic Networks–On-Chip

We report the fabrication and experimental verification of a multiwavelength high-speed 2$, times ,$ 2 silicon photonic switch for ultrahigh-bandwidth message routing in optical on-chip networks. The structure employs only two microring resonators in order to implement the bar and cross states of the switch. These states are toggled using an optical pump at 1.5-$mu$m wavelengths inplane with the waveguide devices, though electronic, rather than optical, control schemes are envisioned for more complex systems built from these devices. Experiments characterize bit-error-rate performance in the bar and cross states during static and dynamic operation. The all-optical demonstration exhibits the ability of the switch to implement ultra-short transition times ( $≪ $2 ns), high extinction ratios ($>$10 dB), and low power penalties (${sim} 1$ dB) at a data rate of 10 Gb/s. Further performance improvements are expected by using electronic carrier injection via p-i-n diodes surrounding the ring waveguides. The 2$, times ,$2 switching functionality facilitates the design of more complex routing structures, allowing the implementation of high-functionality integrated optical networks.