双向可控硅静电防护器件中p型井对静电性能影响的研究

基于0.18μm Bipolar CMOS-DMOS(BCD)工艺,研究讨论了双向可控硅静电防护器件中p型井（PW）位置对器件维持电压以及鲁棒性的静电性能影响,可用于高压静电放电（ESD）保护。利用二维器件仿真平台和传输线脉冲测试系统（TLP）,预测和验证了PW的尺寸在高压工艺下对双向对称可控硅性能的影响。测量结果表明,在不增加器件面积的情况下,通过高压对称DDSCR器件PW层次的左侧边界位置缩进,所得的DDSCR＿PW器件的正向维持电压（Vh）虽然从30.15 V降低到15.63 V,反向维持电压从26.15 V降低到16.85 V,但与高压对称DDSCR器件相比,高压对称DDSCR＿PW器件具有提升失效电流的优点,其正向失效电流从6.68 A增加到18.22 A,反向失效电流从7.07 A增加到9.92A,论文阐述了产生此现象的原因。     

一种多电源域专用数字电路的静电失效分析及提升研究

在静电放电(ESD)能力考核时,一种多电源域专用数字电路在人体模型(HBM)1 700 V时失效。通过HBM测试、激光束电阻异常侦测(OBIRCH)失效分析方法,定位出静电试验后失效位置。根据失效分析结果并结合理论分析,失效是静电二极管的反向静电能力弱所致。利用晶体管替换静电二极管,并对OUT2端口的内部进行静电版图优化设计。改版后,该电路的ESD防护能力达2 500 V以上。该项研究结果对于多电源域专用数字电路的ESD失效分析及能力提升具有参考价值。     

基于工业数据挖掘的ESD软失效分析

针对电子产品出货后出现ESD软失效而导致的退货现象,文章通过机器学习算法分析产品ICT电性能测试参数、生产线ESD防护监控数据和产品ESD软失效的相关性。集成算法模型经过优化,分类准确率达到0.88,可以用于量产电子产品的ESD软失效的识别和出货风险管控。同时,利用ESD防护监控点风险指数数据集可以提高产品ESD软失效的识别准确率（8.6%）。安装部署基于物联网技术的静电放电防护监控系统,对管控电子产品生产过程中的ESD软失效风险以及控制出货风险是很有帮助的,可以提高电子制造业防静电管控的智慧化水平。     

高压GGNMOS器件结构及工艺对ESD防护特性的影响

基于高压CMOS工艺,对高压栅极接地N型金属氧化物半导体（Highvoltagegrounded-gate N-metal-oxide-semiconductor, HV-GGNMOS）的静电放电（Electrostatic discharge, ESD）防护性能进行研究。由于强折回特性以及失效电流低,HV-GGNMOS在实际应用中受到限制。本文通过计算机辅助设计技术仿真及传输线脉冲实验研究了工艺参数及版图结构对器件ESD防护性能的影响。结果表明,增加漂移区掺杂浓度可以有效提高器件失效电流;加强体接触和增加漂移区长度可以提高器件的维持电压,但失效电流会有所下降,占用版图面积也会更大。     

宽带低噪声放大器与ESD防护的协同设计

基于0.18 μm CMOS工艺,介绍了一种UHF频段低噪声放大器(LNA)与静电放电(ESD)保护器件的协同设计和电路仿真方法.采用传输线脉冲测试系统,测得ESD二极管的正向热失效击穿电流为4.28 A,等效于人体模型5.6 kV;反向热失效击穿电流为0.2A,等效于人体模型500 V.通过仿真,分析了ESD二极管的电阻、电容特性,给出了其在LNA正常工作情况下的等效电路;结合LNA电路仿真结果,比较了二极管寄生效应对LNA阻抗匹配、增益、噪声系数和线性度等指标的影响,验证了等效电路的正确性.     

双界面智能卡芯片模拟前端ESD设计

双界面智能卡芯片静电放电(ESD)可靠性的关键是模拟前端(AFE)模块的ESD可靠性设计,如果按照代工厂发布的ESD设计规则设计,AFE模块的版图面积将非常大.针对双界面智能卡芯片AFE电路结构特点和失效机理,设计了一系列ESD测试结构.通过对这些结构的流片和测试分析,研究了器件设计参数和电路设计结构对双界面智能卡芯片ESD性能的影响.定制了适用于双界面智能卡芯片AFE模块设计的ESD设计规则,实现对ESD器件和AFE内核电路敏感结构的面积优化,最终成功缩小了AFE版图面积,降低了芯片加工成本,并且芯片通过了8 000 V人体模型(HBM) ESD测试.     

防静电工作表面：发展和历史（八）

作为对这些改变的响应,一个关键的ESD标准委员会修改了工作表面的测试标准,要求湿度的报告而不是符合特定的湿度规范。这个测试为静电放电敏感物体防护的ESD协会标准测试方法：工作表面-电阻测量,ESDS4．1—1997．更新的测试标准1999年签署,要求在15％RH和其他湿度条件下还是ANSI／ESDS20．20-1999．电气和电子部件、装配和设备（不包括电子引爆爆炸装置）防护静电放电控制程序开发的ESD协会标准,没有ESD工作台资格认证。     

LDMOS器件软失效分析及优化设计

横向扩散金属氧化物半导体(LDMOS)器件在高压静电放电(ESD)防护过程中易因软失效而降低ESD鲁棒性。基于0.25μm Bipolar-CMOS-DMOS工艺分析了LDMOS器件发生软失效的物理机理,并提出了增强ESD鲁棒性的版图优化方法。首先制备了含N型轻掺杂漏版图的LDMOS器件,传输线脉冲(TLP)测试表明,器件在ESD应力下触发后一旦回滞即发生软失效,漏电流从2.19×10-9 A缓慢增至7.70×10-8 A。接着,对LDMOS器件内部电流密度、空间电荷及电场的分布进行了仿真,通过对比发现电场诱导的体穿通是引起软失效及漏电流增大的主要原因。最后,用深注入的N阱替代N型轻掺杂漏版图制备了LDMOS器件,TLP测试和仿真结果均表明,抑制的体穿通能有效削弱软失效,使其适用于高压功率集成电路的ESD防护。     

应用于高压接口电路的SCR ESD保护研究

SCR是ESD保护器件中最具有面积优势的一种。提出一种应用于高压接口电路的SCR ESD保护结构,同时避免了发生闩锁的风险。采用0.5μm BCD工艺设计,可达8000 V人体模型ESD能力,其维持电压可以达到28 V以上。     

ESD的防护策略

通过对现行的一些ESD防护方案的分析,发现了它们的缺陷：对电气应力与静电放电区分不清,系统未能有效地识别：提出了确立防护方案的基本条件：明确系统的防护等级,遵从各类标准的性能指标要求,实施ESD管理.并结合生产的实际情况,从防护等级的确立、数据的获取、装置的监控、防护措施的确定以及防护方案的实施,讨论了工业生产中的ESD防护;从包装材料的筛选、包装的检查、包装标注和测试,分析了ESD防护包装的具体实现;从工作面、工作间的测试和接地的有效搭接,研究了ESD的防护与控制策略.     

一种提高ESD性能的高压SBD器件结构研究

提出了一种新型SBD器件结构,并应用于高压SBD产品的研制。该结构通过在肖特基势垒区的硅表面增加一层表面缓冲掺杂层(Improved Surface Buffer Dope),将高压SBD的击穿点从常规结构的PN结保护环区域转移到平坦的肖特基势垒区,从根本上提高了器件的反向静电放电(ESD)和浪涌冲击能力。经流片验证,采用该结构的10A150VSBD产品和10A200VSBD产品均通过了反向静电放电(HBM模式)8kV的考核,达到目前业界领先水平。该结构工艺实现简单,可以应用于100V以上SBD的批量生产。     

A fully on-chip ESD protection UWB-band low noise amplifier using GaAs enhancement-mode dual-gate pHEMT technology

This paper presents the development of a novel ESD protected wideband low noise amplifier (LNA) using enhancement-mode (E-mode) pHEMT dual-gate clamps. The proposed novel clamp possesses a low on-state resistance, uniform parasitic capacitance, and flexibility to adjust the trigger voltage for different ESD applications. Implementation of the LNA demonstrates that RF performance can be maintained after human body mode (HBM) ESD test while at the same time endure more than +2.5 kV and −2 kV HBM ESD stress voltage. In addition, the incorporated clamps use a fewer number of diodes than the conventional diode stacks, thereby making it size efficient and low effort impedance matching co-design which allow this approach to be an attractive solution for ESD protection.     

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.     

A low-voltage triggering SCR for on-chip ESD protection at outputand input pads

A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V     

基于人体起电实验外推超低电压研究

随着电子工业技术的飞速发展,电子产品静电放电(electrostatic discharge,ESD)敏感度电压已经低于人体模型(human body model,HBM)电压50 V,然而现有防静电工作区(electrostatic discharge protected area,EPA)配置要求标准只是针对于ES...     

On a dual-polarity on-chip electrostatic discharge protectionstructure

A novel dual-polarity on-chip electrostatic discharge (ESD) protection structure is designed. The new ESD structure protects IC chips against ESD stressing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for overvoltage clamping, fast ESD response of ~0.18 ns, low leakage (~pA), adjustable triggering voltage, and good scalability. It passes 14 KV HBM ESD zapping tests and achieves high ESD-performance-to-Si ratio of ~80 V/μm width. The new ESD structure reduces Si areas consumed by ESD protection units and ESD-induced parasitic effects significantly     

Robust PIN photodiode with a guard ring protection structure

A guard ring (GR) structure is used to protect a planar InGaAs pin photodiode. The human body model (HBM) measurement results show that a photodiode with a GR, which is shorted to the cathode, is able to withstand an electrostatic discharge (ESD) threshold voltage of up to 200 V, whereas a similar photodiode without a GR structure can only withstand 50 V ESD threshold voltage. The capacitance and bandwidth measurement results show that the GR has negligible negative effects on the pin diode performance.     

集成电路闩锁效应测试

CMOS制程是现今集成电路产品所采用的主流制程。闩锁效应(Latch-up)是指CMOS器件中寄生硅控整流器(SCR)被触发导通后,所引发的正反馈过电流现象。过电流的持续增加将使集成电路产品烧毁。闩锁效应已成为CMOS集成电路在实际应用中主要失效的原因之一。在国际上,EIA/JEDEC协会在1997年也制订出了半静态的闩锁效应测量标准,但只作为草案,并没有正式作为标准公布。我们国家在这方面还没有一个统一的测量标准,大家都是在JEDEC标准的指导下进行测量。文章针对目前国际上通行的闩锁效应测试方法作一个简要的介绍和研究。     

Analysis of ESD protection structure behaviour after ageing as new approach for system level reliability of automotive power devices

ESD (electrostatic discharge) protection devices as part of the device pad circuitry of semiconductors are designed for a specific wafer technology and ESD withstanding voltage. After successful qualification they will be released for a usage in high volume products where they must ensure the ESD robustness over the complete product lifetime.All present automotive qualification standards e.g. AEC (automotive electronic council) or JEDEC do not cover the assessment of the typical drifts of the characteristic electrical ESD protection device parameters after application of device specific reliability stress tests under consideration of the target ESD stress [Automotive Electronic Council, AEC-Q100-Rev-F, 2003; Automotive Electronic Council, AEC-Q101-Rev-C, 2005; JEDEC JP-001, Foundry Process Qualification Guideline, 2002].The paper introduces a methodology to characterize ESD protection diodes after ageing by BTS (bias temperature stress) reliability tests. The used devices are partly ESD pre-stressed before application of the reliability test. The influence of the reliability stress on the ESD robustness is evaluated by using an ESD post-stress.The experimental results are presented and discussed. For ESD protection devices release targets for automotive power applications are defined.     

Test structures and testing methods for electrostatic discharge: results of PROPHECY project

The goal of one PROPHECY subtask was to find a set of realistic test patterns for electrostatic discharge (ESD) and propose an appropriate testing method. Starting with basic test structures, a systematic analysis of the layout parameters dependence of the ESD hardness of various CMOS technologies tested according to the Human Body Model (HBM), Transmission Line Pulser (TLP) and socketed Charged Device Model (CDM) hardness has been carried out. Main emphasis has been given to the correlation between results obtained by the different test methods i.e. HBM and TLP, as well as between HBM and socketed CDM. The results obtained on the basic test structures, which are representative of an analogue technology, are compared (i) with results on optimised test patterns, which more realistically emulate the structure of the actual integrated circuits, and (ii), finally with results on several products. It is shown that the results of a careful analysis of the test patterns can be applied to real pads, and at the end, even to products.