一种0.6 V低压两级时间数字转换器

研究了用于超低功耗全数字锁相环(ADPLL)的时间数字转换器(TDC)在近阈值电源电压下的工作原理,提出了一种近阈值电压时间转换器。采用两级量化的TDC,通过时间放大器对量化余量进行放大,实现二次量化。针对TDC低压下的功耗、速度问题,实现了一种增益可扩展的时间放大器,提高了时间分辨率。基于130 nm CMOS工艺的仿真结果表明,两级量化时间数字转换器的分辨率为2.5 ps,动态范围为640 ps,微分非线性(DNL)最大值为0.9 LSB,积分非线性(INL)最大值为2.3 LSB。4倍时间放大器的增益误差为8.2%。     

基于新型时间放大器流水线时间数字转换器

针对传统时间数字转换器(TDC)中普遍存在的转换速度与转换精确度相互制约问题,提出一种适用于流水线型TDC结构的新型边沿对准时间放大器。这种时间放大器采用三级门控延时链与边沿合成器的级联结构,可实现增益为4的整数倍时间放大。在0.35 μm标准CMOS工艺下完成整体流水线型TDC的设计,仿真结果显示,输入动态范围为6.11 ns,时间分辨力为13.1 ps,转换速率为50 MSamples/s。相比于传统基于脉冲序列时间放大器的TDC,转换速率提高19.5%,精确度提高33.7%。     

基于FPGA的高精度多通道时间数字转换器设计

采用Xilinx Virtex-5 FPGA芯片,实现了一种高精度、多通道时间数字转换器的设计。每个通道配有一条抽头延迟线,每条延迟线由64个快速超前进位链(CARRY4)组成。布线后,延迟线成链状结构紧密排列,有效消除了布线路径带来的误差,降低了积分非线性和微分非线性误差。仿真结果表明,设计的时间数字转换器的最低有效位约为26.35 ps,有效精度约为14 ps,INL小于4.3 LSB,DNL在-0.8 LSB~2.4 LSB范围内。     

一种基于三态反相器的高精度时间放大器

传统的基于三态反相器设计的时间放大器(TDA)具有电路复杂度低、对电压余度和温度的影响不敏感的特点,但该结构的时间分辨率低,增益误差大,应用范围相对较窄.本文提出一种改进的时间放大器结构,通过重新设计延迟链控制信号产生电路以实现高精度增益的要求.基于40 nm CMOS工艺进行Spectre仿真结果表明,本文提出的TDA结构不仅具有稳定可控的增益(增益误差保持在±4%以下)和高时间分辨率(380 fs),而且输入范围得到进一步提升.     

一种基于平均电阻网络的预放大级设计

平均电阻网路的引入会给预放大器带来增益、延时误差、边界效应等问题。通过从中间向两边依次增加预放大器输入对管的尺寸,减小整体误差。通过改变环形平均电阻的边界阻值和边缘放大器的输入参考电压,减小边界效应,并且使用的边缘放大器数目较少。采用TSMC 0.18 μm标准CMOS工艺,在1.8 V电源电压下,对加入平均电阻网络的ADC的输出进行仿真,得到INL为1.01 LSB、DNL为0.573 LSB。对改变输入对管尺寸的ADC整体电路进行DFT分析,得到ENOB为11.14 bit、SFDR为76.3 dB、THD为-78 dB。采用减小边界效应的方法,对边界预放大器进行蒙特卡洛仿真,结果表明,失调电压方差从2.193 mV减小到0.456 mV。     

高精度宽带数字控制可变增益放大器的设计

设计了一种高精度宽带数字控制可变增益放大器,利用增益加强技术改进可变增益放大器的步进精度;同时,引入零点抵消技术,并加入源极负反馈电容,在不增加额外功耗的条件下,拓展了带宽。该电路采用0.18μm CMOS工艺,1.8V供电电源,增益动态范围为62dB,步进精度为1dB,步进误差为0.2dB。设计的可变增益放大器可以提供高达80MHz的带宽,整个电路消耗1.5mA电流,芯片尺寸为300μm×800μm。     

应用于PWM降压DC-DC变换器的高性能误差放大器

提出了一种应用于PWM降压型DC-DC变换器的高性能误差放大器。该误差放大器采用反馈结构,具有较大的动态范围,并可消除噪声影响,从而显著减小了DC-DC电源的纹波电压。另外,采用该误差放大器还有效地减小了电源启动时间。文中提出的误差放大器电路及PWM控制芯片的其他电路模块采用2.0μmBipolar工艺实现。仿真结果表明,误差放大器的开环和闭环增益分别为61dB和33dB,GBW为200MHz,SR为0.64V/μs。芯片测试结果表明,在输出电压为3.3V,负载电流为0.2A时,输出纹波电压的峰-峰值小于25mV。     

半导体光放大器的超快动态增益特性

提出了一种包括载流子密度脉动(CDP)、载流子加热(CH)和光谱烧孔(SHB)效应在内的半导体光放大器(SOA)的时域动态模型。利用该模型分析了半导体光放大器中的增益饱和、超快增益动态以及光脉冲在增益饱和半导体光放大器中的波形畸变,其中重点考虑了超短脉冲的情况。模拟计算表明,对于10ps量级以下的短脉冲,分析半导体光放大器的动态增益特性时,不能忽略载流子加热和光谱烧孔等带内超快非线性效应的影响。     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

基于HgCdTe-APD的32×32主被动成像读出电路

设计了一款基于线性模式下HgCdTe-APD的主被动双模式读出电路。被动模式下通过积分电容进行光信号的强度测量,主动模式下利用两段式TDC进行光子飞行时间(ToF)的标记。TDC采用面阵共享的数字计数器进行粗计数,像元内置时间幅度转换电路(TAC)进行精细测量,同时利用积分电容的切换修正时刻鉴别误差。焦平面阵列规模为32×32,工作温度为77 K,采用标准SMIC 0.18μm CMOS工艺进行电路设计及版图绘制。仿真验证结果显示,电路满阱容量约为7.5 Me^-,在3.2μs的动态范围ToF分辨率小于0.5 ns, DNL和INL分别在-0.15 LSB～0.15 LSB和-0.2 LSB～0.2 LSB范围内。读出电路帧频为4.5 kHz,功耗小于180 mW。     

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.     

A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under /spl plusmn/0.20 LSB and INL less than /spl plusmn/0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.     

一种新颖的低非线性全数字多相时钟产生电路

通过对传统的全数字多相位时钟产生电路进行分析和总结,提出一种新颖的延时校准算法。该算法通过优化调整延时单元的顺序,大大改善了全数字多相位时钟产生电路的非线性。整个电路基于全数字延迟锁相环,采用0.13μm CMOS工艺实现,并成功用于时间数字转换器中。输入时钟频率范围在110 MHz到140 MH间,对应的输出相位差为446 ps到568 ps,积分非线性小于0.35 LSB,微分非线性小于0.33 LSB。     

A four-input beam-forming downconverter for adaptive antennas

A four-input beam-forming downconverter for adaptive antennas is described. It consists of 2-bit variable gain amplifiers (VGAs), 5-bit local oscillator (LO) signal phase shifters using double RC-bridge circuits, and mixers. The VGAs adjust gain deviation between signal paths. A differential-signal-to-eight-phase-signal converter is employed as a part of the LO phase shifter to reduce the chip size. A maximum phase error of 4.1/spl deg/, which is less than 1/2 LSB, is achieved. This error value indicates that the required phase shifter accuracy and the necessary isolation between the VGAs has been achieved. This beam-forming IC is applicable to receivers with adaptive antennas, and is expected to help to reduce the costs of adaptive antenna systems.     

A new hybrid TDC based on GRO-pseudo delay architecture with fractional code and wide time range detection for divider-less ADPLL

This paper presents a novel Time-to-digital converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a gated ring oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. The proposed TDC is designed in 90 nm CMOS process. Simulation results show that the TDC achieves a large detectable conversion range that extends between 0.285 and 10 ns. The attained time resolution is 9.4 ps, which corresponds to half the delay time of an inverter. The TDC is self-calibrating with estimated accuracy better than 0.28%. The structure consumes 6.6 mA current from a 1.0 V voltage supply, when operating at a clock frequency of 13 MSPS. The estimated differential nonlinearity and integral nonlinearity are ±0.48 LSB and ±0.6 LSB respectively. Compared to previously reported TDC, this implementation achieves a competitive FoM_P without requiring complicate calibration.     

A fast-lock mixed-mode DLL using a 2-b SAR algorithm

In this paper, a fast-lock mixed-mode delay-locked loop (MMDLL) is presented. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve short lock time compared to the conventional RDLL, CDLL, and SARDLL, while the analog part helps to reduce the residue phase error introduced by the digital part and improve the output jitter performance. The measured RMS and peak-to-peak jitters and the static phase error are 6.6, 47, and 12.4 ps, respectively, for a 100-MHz input clock. The power consumption is 15.8 mW in the locked state at a 2.7-V supply voltage. The maximum lock time is 13.5 clock cycles (135 ns) when the residue phase error is within 1 LSB (156 ps)     

A CMOS time to digital converter IC with 2 level analog CAM

A time to charge converter IC with an analog memory unit (TCCAMU) has been designed and fabricated in HP's CMOS 1.2-μm n-well process. The TCCAMU is an event driven system designed for front end data acquisition in high energy physics experiments. The chip includes a time to charge converter, analog Level 1 and Level 2 associative memories for input pipelining and data filtering, and an A/D converter. The intervals measured and digitized range from 8-24 ns. Testing of the fabricated chip resulted in an LSB width of 107 ps, a typical differential nonlinearity of <35 ps, and a typical integral nonlinearity of <200 ps. The average power dissipation is 8.28 mW per channel. By counting the reference clock, a time resolution of 107 ps over ~1 s range could be realized     

Optical True Time-Delay for Two-Dimensional X -Band Phased Array Antennas

An optical true time-delay (TTD) scheme for two-dimensional (2-D) X-band phased array antennas (PAAs) has been proposed. It is composed of a multiwavelength optical source and a delay line matrix consisting of 2times2 optical microelectromechanical system (MEMS) switches with fiber-optic delay lines connected between cross ports. A 2-bit times 4-bit optical TTD for 10-GHz 2-D PAAs has been implemented by cascading a wavelength-dependent TTD (WD-TTD) with a unit time delay of 12 ps in the x-direction and a wavelength-independent TTD (WI-TTD) with that of 6 ps in the y-direction. The time delay error for WD-TTD was measured to be less than 2.8 ps, mainly due to jitter incurred from gain-switching. On the other hand, the error for WI-TTD was less than 0.8 ps, which is within the equipment resolution. Insertion loss of both delay line matrices was less than 1 dB due to the column-wise control of the MEMS switches. This prevents the feed current applied to each antenna element from fluctuating at any radiation angles so that antenna gain and sidelobe level do not deteriorate in this scheme