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两种低功耗新型过温保护电路的设计 总被引:2,自引:0,他引:2
电源管理芯片中过温保护电路用来检测芯片的温度。当温度过高时,过温保护电路输出保护信号,使芯片停止工作,以免温度过高而损坏芯片。为了实现上述过温保护电路功能,提出了两种新型的过温保护电路,不但能够精确地检测芯片的温度,并且功耗很低。采用0.5μm N-阱CMOS工艺的方法,进行电路设计,并使用CadenceSpectre工具进行了仿真实验验证。仿真实验结果表明两种电路仅消耗3μA的电流就能够实现精确的温度检测,其具有较强的适应性,高灵敏度和高精度的特点,应用前景比较广泛。 相似文献
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设计了一种用于GaN HEMT器件栅驱动芯片的高性能温度保护电路,能精确响应并输出保护信号以确保电路安全.过温保护采用两路温度检测电路来采集温度信号电压值并对电压差值进行放大,比较滤波后经过具有滞回功能的施密特触发器输出整形保护信号,可以克服共模噪声和温度应力的影响.基于CSMC 0.18μm BCD工艺,完成了电路设计验证与测试,结果显示电路功能正确,可满足GaN HEMT器件栅驱动芯片应用要求. 相似文献
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由于芯片集成度的提高,改善电路性能的同时也导致功率密度增加.为了防止芯片过热,保证芯片可靠、稳定的工作,设计了一款基于电流比较的新型过温保护电路.电路通过产生与绝对温度(正/负温度系数PTAT/CTAT)相关的电流并进行电流比较,输出包含温度信息的逻辑控制信号,实现对芯片工作状态的控制.对电路的工作原理进行了详细的分析和推导,并给出了电路中核心器件的参数设置.基于UMC 0.6 μm BiCMOS工艺进行了流片并对电路进行了测量,热关断、开启温度分别为125℃和114℃,具有1 1℃的温度滞回量;转换速率26.2 V/℃,具有高灵敏度、高精度的特点;当供电电压发生变化时,电路性能稳定,具有较好的应用前景. 相似文献
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为保证系统在热插拔过程中安全工作,避免因之导致系统崩溃及系统与部件的损坏,提出一种热插拔控制芯片的设计.针对热插拔过程中可能产生的浪涌电流和过流、过压等故障现象,芯片设计中设置了多重保护功能,包括自动限制启动电流,过流时切断电路以及过压时断电,长时过压触发SCR为负载提供撬棒保护等.另外,设计了低压诊断、负载电压等检测功能.由于芯片工作中涉及较高电压和较大电流,电路采用BCD工艺(bipolar-CMOS-DMOS)实现,并对系统、电路和版图进行了优化.制得的芯片面积约为2.5mm×2.0mm,可在4.5~16.5V电压范围内正常工作,12.0V电源电压下芯片功耗约为18mW.对芯片的测试结果表明,所设计的电路功能和特性已成功实现. 相似文献
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为了防止芯片过热,提高芯片可靠性和稳定性,提出了一种改进的高精度、低功耗、具有迟滞功能且结构简单的过温保护电路。在不引入热振荡的前提下,实现稳定电路温度和输出关断信号的双重功能。阐述了过温保护电路的工作原理,基于先锋国际半导体公司的BiCMOS0.5μm工艺库模型进行电路设计,采用Hspice软件并用先锋国际半导体公司的BiCMOS 0.5μm工艺库模型对该电路进行模拟仿真。仿真结果表明:当外界温度达到137℃时,过温保护电路输出发生翻转,从而关断芯片内的其他电路,降低功耗,使温度降低。当温度降到120℃时,芯片回到正常工作状态,温度迟滞量为17℃,性能稳定可靠。 相似文献
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《Microwave Theory and Techniques》1980,28(5):500-508
An ac power system design in described for powering, at near gigahertz frequencies, 16K Josephson latching logic circuits distributed uniformly over 16 chips. The power system distributes a sinusoidal current waveform from a single source to the many chip quadrants through a tree system of thin-film transformers that have branching secondaries and multiple turn primaries to maintain nearly constant current amplitudes throughout the system and small phase skews at the logic-circuit level. The sinusoidal waveform is clipped on-chip to provide the trapezoidal waveform required by the logic circuits. The ratio of the duration of the up-portion of the trapezoidal half-cycle to the half-cycle period (the logic cycle) is defined as the active duty cycle for the logic. The 16K circuit-power design is capable of providing an 80-percent duty cycle at a 1.7-ns logic cycle while keeping current levels in the system below 300 mA. An approximate expression is derived that predicts that for any power-system design of this type the product of the system size, the highest frequency of operation, and the chip-quadrant current level is a constant. 相似文献
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Wilson C.D. O'Neill A.G. Baier S.M. Nohava J.C. 《Electron Devices, IEEE Transactions on》1996,43(2):201-206
The high temperature performance of Al0.75Ga0.25 As/In0.25Ga0.75As/GaAs Complementary Heterojunction FETs (CHFETs) is reported between 25 and 500°C. Both experimental and modeled devices have shown acceptable digital characteristics to 400°C. Digital logic circuits have also been shown to operate at temperatures of over 400°C. This strongly suggests that GaAs based devices are capable of satisfying high temperature electronics requirements in the 125-400°C range. Two dimensional physically based modeling has been used to understand the high temperature operation of the HFETs. This work has shown that the devices suffer from gate limited drain leakage currents at elevated ambient temperatures. This off-state leakage current is higher than anticipated. Simulation has shown that, although forward gate leakage currents are reduced with the heterostructure device design, the reverse current is not 相似文献
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基于PWLL结构的占空比矫正电路虽然克服了传统占空比矫正电路输出时钟上升沿在占空比矫正过程中发生变化的缺点,但其核心电路——频率电压变换电路不能工作在100MHz以上的频率范围,并且随着工作频率的升高,调整范围会变小。采用pullpush电荷泵代替频率电压变换电路,设计了一个工作在200MHz的占空比矫正电路,HSPICE仿真结果表明其调整范围为30%~70%,占空比变化在1个ps以下,达到了设计要求。 相似文献
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Hong-Yi Huang Jing-Fu Lin 《Solid-State Circuits, IEEE Journal of》2004,39(8):1305-1312
This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V. 相似文献
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在介绍ICL8038工作原理及管脚功能的基础上,对其内部电路进行了详细分析,提出减小波形传输时间的方法。通过OrCAD 9.2对其内部电路进行晶体管级仿真,其结果表明,在触发器模块电路中采用抗饱和晶体管可提高电平翻转速度,且输出波形的频率和占空比可由电流或外围电阻控制。进一步分析证明,ICL8038具有精度高,误差小等优点,因此在各种工业自动化控制中具有巨大的应用前景。 相似文献
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This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-Ω toward (VDD-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s 相似文献