An improved low offset latch comparator for high-speed ADCs

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW.     

A high-speed latched comparator with low offset voltage and low dissipation

An ultra high-speed latched comparator using a controlled amount of positive feedback cell has been designed in TSMC 0.18 μm CMOS technique. Transmission gate (TG) switches are used to implement the preamplifier circuit. The use of TG switches results in a reduction in the power consumption of the high-speed comparator as well as clock feedthrough and the effect of charge injection. The simulation results demonstrate that it can work at 1.25 GHz suitable for high speed applications, and consumes 273.6 μW with a power supply of 1.8 V at 100 MHz and Monte Carlo simulation shows that the comparator has a low offset voltage approximately 0.499 mV.     

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.     

An offset cancellation technique for comparators using body-voltage trimming

A novel offset cancellation technique based on body-voltage trimming is presented to be used in the comparators employed in high-speed analog-to-digital converters (ADCs) such as Flash ADCs. The proposed offset cancellation is achieved by body-voltage adjustment using a low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output or complicated digital calibration scheme. The accuracy of the proposed technique is higher than its digital calibration counterparts due to its analog nature. Simulation results in a 1.8?V 0.18???m CMOS technology show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 36.2 to 7.1?mV operating at 1?GHz with only 32???W of power dissipation in the offset cancellation circuit.     

一种高电源效率开关电流比较器

提出了一种基于Boonsobhak结构但电源效率更高的开关电流比较器。比较器采用主从式结构,工作模式由两相不交叠时钟控制。主比较器根据输入电流信号的极性产生微小电压差,同时将输出信号对输入信号的影响隔离开来。从比较器将主比较器产生的微小电压差进行再生放大,最终产生比较结果。提出的新比较器结构采用静态甲乙类锁存式比较器作为主比较器,以静态功耗为零的动态锁存式比较器为从比较器,使得整体比较器在保持较高速度的同时,功耗大为降低。采用CSMC0.6μmCMOS工艺设计并实现,实际测试结果显示开关电流比较器具有6.5bit分辨率,能在20MHz时钟频率下正常工作,而功耗降低了75%。     

一种高速高精度比较器的设计

基于预放大锁存快速比较理论,提出了一种高速高精度CMOS比较器的电路拓扑.该比较器采用负载管并联负电阻的方式提高预放大器增益,以降低失调电压.采用预设静态电流的方式提高再生锁存级的再生能力,以提高比较器的速度.在TSMC0.18μm工艺模型下,采用Cadence Specture进行仿真.结果表明,该比较器在时钟频率为1GHz时,分辨率可以达到0.6mV,传输延迟时间为320ps,功耗为1mW.     

5位高速低功耗Binary-Search模数转换器

基于65 nm CMOS工艺,设计了一种高速低功耗二分搜索算法(Binary-Search)模数转换器(ADC)。与传统Binary-Search结构相比,该ADC的比较器采用两级动态前置放大器和一级动态闩锁器组合构成,减小了静态电流,得到极低的功耗;失调电压降低到不会引起判决误差,省去了外接的数字校准模块。因此,芯片面积减小,避免了校准模块拖慢比较器的工作速度。后仿结果表明,当采样频率为1 GHz时,该Binary-Search ADC的有效位达4.59 bit,功耗仅1.57 mW。     

A 84% tuning range, 4.3-GHz VCO with two-step negative-G<Subscript>m</Subscript> tuning and amplitude calibration loop

This paper presents wideband, low voltage CMOS LC-VCO with automatic two-step amplitude calibration loop to compensate the PVT variation. To cover the wide tuning range, digital automatic negative-G_m tuning loop and analog automatic amplitude calibration loop are proposed. The power consumption is 2–6 mA from a 1.2 V supply. The VCO tuning range is 3.4 GHz, from 2.35 to 5.75 GHz. The measured phase noise is −117 dBc/Hz at the 1 MHz offset when the center frequency is 4.313 GHz.     

An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch

This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch comparator. Two analytical models are presented and compared with HSpice simulations. Our results indicate that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of several tens of millivolts     

一种高速开关电容动态锁存比较器分析与设计

设计了一种基于CMOS工艺的开关电容动态锁存比较器。该比较器包含一个共模不敏感全差分开关电容采样级和一级动态锁存比较器。开关电容采样级验证了比较器的输入共模范围,动态锁存器采用两个正反馈锁存器和额外的反馈环路提高了锁存的速度。基于0.18μm 1.8V CMOS工艺进行了版图设计和后仿真,结果表明该比较器可以应用于200 MSPS高精度流水线模数转换器。     

Low power time-domain rail-to-rail comparator with a new delay element for ADC applications

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step.     

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.     

低功耗高精度的电压比较器设计

设计了一款用于实现10位精度逐次逼近型模数转换器(SAR ADC)的电压比较器,该比较器采用高速高精度比较器结构并进行了优化,在高速度、低功耗锁存器的基础上加预放大级以提高比较精度,加RS触发器优化处理比较器的输出信号。同时,采用失调校准技术消除失调,预放大级采用共源共栅结构抑制回程噪声,最终获得了高精度和较低的功耗。仿真结果表明:在Chartered 0.35μm 2P4MCMOS工艺下,时钟频率5 MHz,电源电压3.3 V,分辨率达0.1 mV,平均功耗约为0.45 mW,芯片测试结果表明比较器满足了SAR ADC的要求。     

CMOS charge-transfer preamplifier for offset-fluctuationcancellation in low-power A/D converters

We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-μm CMOS process. Low differential nonlinearity of less than ±4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 μW per MS/s per comparator has also been achieved     

A high-speed CMOS comparator with 8-b resolution

A comparator consisting of a differential input stage, two regenerative flip-flops, and an S-R latch is presented. No offset cancellation is exploited, which reduces the power consumption as well as the die area and increases the comparison speed. An experimental version of the comparator has been integrated in a standard double-poly double-metal 1.5-μm n-well process with a die area of only 140×100 μm². This circuit, operating under a +2.5/-2.5-V power supply, performs comparison to a precision of 8 b with a symmetrical input dynamic range of 2.5 V (therefore ±0.5 LSB resolution is equal to ±4.9 mV)     

An Offset Compensated Sampled-Data CMOS Comparator Circuit for Low-Power Implantable Biosensor Applications

This paper proposes a new low-voltage high resolution complementary metal oxide semiconductor (CMOS) comparator circuit suitable for biosensor applications. The comparator compensates for differential input offset through single-ended sampled-data preamplification. Simulations were carried out using a 130 nm IBM CMOS (CMRF8SF) process technology. Monte Carlo simulations incorporating mismatch between devices (based on width and length of devices) indicate that the design is quite robust. The comparator has a differential input overdrive resolution of under 1 mV and a response time which is scalable. The capacity for offset compensation trades with the bandwidth of the comparator through the size of the device channel areas (Width × Length) of the transistors. The static micropower consumed by the comparator from a 0.5 V supply voltage is under 10 μW, making it extremely suitable for miniaturized implantable biosensor devices. In addition, the comparator uses a single clock scheme for the sampled-data operations, which eliminates the need for special clock generation circuitry.     

A 1?mW power-efficient high frequency CML 2:1 divider

In this study, a low power high operating frequency current mode logic (CML) 2:1 divider is presented. Because the latching transistor pair is biased in low current mode, the proposed divider is power-saving. In this divider, each latch has only one clock transistor, which means that the capacitive load to the former stages is reduced. This makes the buffer of the voltage controlled oscillator (VCO) or VCO be easily designed in phase locked loops. Besides, an active inductor is used in this circuit to resonate with parasitic capacitances and thus endows this topology a high-speed capability. The measurement results indicate that the proposed divider achieves an operation band from 10 to 15?GHz with only 1mW power dissipation.     

An 8-bit 12.5-GSample/s SiGe ADC

This paper describes the design of a high-speed 8-bit Analog to digital converter (ADC) used in direct IF sampling receivers for satellite communication systems in a 0.25 μm, 190 GHz SiGe BiCMOS process. A high resolution front-end track-and-hold amplifier (THA), a low impedance reference and interpolation resistive ladder and high resolution comparators enable the ADC to achieve good performance for input frequencies of up to one-quarter of the sampling rate. The final post layout simulated system features an ENOB of 7.2-bits at an input frequency of 3.125 GHz and a sampling rate of 12.5 GS/s with a FOM of 12.9 pJ per conversion. Both DNL and INL are within 0.5 and 1 LSB, respectively. The converter occupies 10 mm² and dissipates 14 W from a 3.3 V supply. The THA and the comparator, as the most critical building blocks affecting the overall performance of the ADC, were implemented experimentally and fully characterized in order to verify their performance and to ascertain the possibility of implementing the complete ADC. The THA occupies an area of 0.5 mm². It features a SNDR of 47 dB or 7.5-bits ENOB for a 3 GHz bandwidth, a hold time of 21 ps with a droop rate of 11 mV/80 ps and a power dissipation of 230 mW from a 3.3 V supply. The comparator occupies an area of 0.38 mm² and exhibits an input sensitivity of ±2 mV, an input offset voltage of 1.5 mV, latch and recovery times of 19 and 21 ps, respectively, and a power dissipation of 150 mW from a 3.3 V supply. The experimental results are in good agreement with simulation and expected specifications and indicate that both circuits are suitable for the implementation of the ADC and help to validate that the 8-bit 12.5 GS/s ADC is feasible for implementation in a 0.25 μm SiGe process.