Submicrometer Electron-Beam Direct Writing Technology for 1-Mbit DRAM Fabrication

A 1-Mbit DRAM with 0.5-/spl mu/m minimum linewidth is fabricated using variable shaped e-beam direct writing technology. A simple linewidth control technique using newly developed submicrometer resists is developed to achieve high resolution and better linewidth accuracy. In addition, a highly accurate registration technique is developed to ensure required overlay. These techniques are successfully used to achieve overlay accuracy of 0.04 /spl mu/m(sigma) and linewidth deviation of 0.018 /spl mu/m(sigma) in the fabrication.     

Trench transistor DRAM cell

A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the polysilicon node surrounded by oxide, the cell is expected to have a high alpha particle immunity. The cell occupies only 9 µm²using 1-µm design rules. This cell size is sufficiently small to enable a 4-Mbit DRAM of reasonable chip size with these design rules, and possesses further scalability for 16-Mbit DRAM's.     

Oxide-Nitride Storage Dielectric Formation in a Single-Furnace Process for Trench DRAM

A simplified and integrated technique has been proposed to form an oxide/nitride storage dielectric in a single-furnace process by low-pressure oxidation and nitride film deposition with an extra$hboxN_2hboxO$treatment for the trench dynamic random access memory (DRAM). Compared to the conventional nitride/oxide dielectric, this newly developed dielectric enjoys cell-capacitance-enhancement factor as high as 12.5% without degrading the leakage current and electron-trapping property. From the reliability test, the qualification for the DRAM application is also proven by the dielectric lifetime longer than 10-years. Most importantly, this technique can reduce the production cycle time without an additional equipment investment, which is essential in the cost-competitive DRAM arena.     

Submicrometer electron-beam direct writing technology for 1-Mbit DRAM fabrication

A 1-Mbit DRAM with 0.5-µm minimum linewidth is fabricated using variable shaped e-beam direct writing technology. A simple linewidth control technique using newly developed submicrometer resists is developed to achieve high resolution and better linewidth accuracy. In addition, a highly accurate registration technique is developed to ensure required overlay. These techniques are successfully used to achieve overlay accuracy of 0.04 µm(σ) and linewidth deviation of 0.018 µm(σ) in the fabrication.     

动态随机存取记忆体的深槽电容器制造方法

首先对深槽电容器应用于4Mb至256Mb动态随机存取记忆体的发展做简要的回顾,以便于读者了解不同时期的记忆体元件设计概念及关键技术。后半部分以示意图方式解析256Mb深槽电容器制造工艺流程,使读者进一步了解先进记忆体产品制造上的主要挑战。     

BST材料在DRAM电容中的应用研究

钛酸锶钡(BST)高介电常数材料被普遍认为是最有前途的DRAM电容介质材料。BST作为DRAM电容介质材料的研究已有多年，到目前为止取得了不少突破性的进展。介绍了BST的材料特性和堆积型电容结构电极、埋层材料的设计考虑，探讨了BST膜的制备、掺杂及刻蚀工艺技术。     

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.     

Conductive Carbon as a Novel Front-End Electrode Material for a Trench DRAM

We report on the electronic properties and application of conductive carbon as a novel front-end material. Conductive carbon is attractive due to its metallic properties, high thermal stability, compatibility to Si-based dielectrics, and the availability of a low-cost batch deposition process. Here, we utilize carbon instead of a polysilicon top electrode in a deep trench capacitor with SiON node dielectric. A capacitance gain of 10% is observed due to suppression of electronic depletion. Furthermore, the midgap work function of 4.4 eV leads to a reduction of leakage currents due to a higher tunneling barrier. This allows electric thinning of the dielectric for a total capacitance gain of 20%, compared to a polysilicon electrode, while maintaining excellent electronic reliability characteristics.      

Process simplification in DRAM manufacturing

DRAM manufacturers are driving the quest for integration friendly, simplified, and statistically-controlled process development. In the DRAM field, strong emphasis must be placed on “process simplification” as a means of staying cost effective and competitive. In order to examine process architecture and process integration, both at the module and system levels, it is emphasized that using correct statistical methods in conjunction with advanced technology is important. For simplified process development and integration, many aspects of the new process assessment are data driven. Also, it is critical to understand the source of variation in the process, obtain process stability, and assess the process capability relative to specifications of manufacturability and functionality. Statistical process control techniques are a requirement for interpreting the results of process capability studies, as will be discussed in this paper. In this paper, we have emphasized that both statistical methods and technological innovation are required for process optimization. We have investigated several examples that illustrate the methodology followed for the development of statistically controlled, production-worthy processes. The process improvement strategy is described both for gate stack and the DRAM cell. The focus of the results described here is both in the context of enhancing process capability for existing processes and evaluating alternate process options that can be accomplished through the use of advanced process technology     

Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

A multistrata dynamic random access memory (DRAM) vertically integrated with a complementary metal oxide semiconductor (CMOS) logic device using through-silicon vias (TSVs) and a unique interposer technology was developed for high-performance, power-efficient, and scalable computing. SMAFTI (SMArt chip connection with FeedThrough Interposer) technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was used for interconnecting the three-dimensionally stacked DRAM and the CMOS logic device . A DRAM-compatible TSV manufacturing process was realized through the use of a “via-first” process and highly doped poly-Si TSVs for vertical traces inside memory dice. A multilayer ultra-thin die stacking process with micro-bump interconnection using a solid-liquid interdiffusion technique was also developed. The thermal aging reliability of the micro-bump interconnection was evaluated by a unique analysis method and its basic reliability was confirmed. Finally, we fabricated a prototype package including stacked DRAM and a CMOS logic device, and observed the combined operation. High-speed 3 Gbit/s signals were successfully transmitted through the fine interposer between the memory and logic.      

Polymeric Waveguide Optical Switch With Bascule Structure Using Novel Trench Forming Process

We develop a polymeric waveguide optical switch with a bascule structure. Our novel matrix switch diverts light from one waveguide to a crossing waveguide in a polymeric waveguide film, using total internal reflection (TIR) of the interface between a waveguide and a trench at the waveguide cross point by mechanical actuation. The key technique for achieving a low-loss property is a novel cleaving method of forming trenches at waveguide cross points. We achieved a loss of 5 dB for the longest path of an 8 times 8 matrix switch demonstrator, high speed switching operation up to 100 mus, and reliable performance over 10 million times switching.     

亚微米器件制造技术的发展动态

主要从光刻隔离,金属互连线三个方面讨论了亚微米器件所面临的挑战及其发展趋势。     

An Optimally Designed Process for Submicrometer MOSFET's

An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET's. Process/device simulation is extensively used to find an optimized processing sequence compatible with typical production-line processes. The simulation results show an excellent agreement with experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5 V, and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 /spl mu/m. The short-channel effects have been also minimized. A new self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.     

深槽介质工艺制作高密度电容技术

随着系统向高速度、低功耗、低电压和多媒体、网络化、移动化的发展,系统对电路的要求越来越高,在需求牵引和技术推动的双重作用下,出现了将整个系统集成在一个微电子芯片上的系统芯片(System On A Chip,SOC)概念。采用SOC的设计方式可以使芯片面积向小尺寸、高集成度方向发展。SOC设计的系统芯片能够得以实现是以不断发展的芯片制造技术为依托的。文章介绍了基于深槽介质工艺制作高密度电容的技术,通过深槽工艺技术实现大的存储电容。该电容制作采用深槽刻蚀、ONO介质、原位掺杂多晶(ISDP)填充等工艺技术,可以增加电容密度达20倍,提高了电路集成度,其性能优良、漏电极低。     

正确使用钽电容器

使用钽电容器时应注意电气、气候、组装和机械、存储等方面的条件。任何一方面的条件不合适，都可能造成短路、漏电流增大等问题。 1 工作电压 电压降额幅度应尽可能大。在常规条件下，工作电压（含纹波电压）Vo应降至额定电压Vr的50%以下，建议降至30%，尤其是用于低阻抗电路时。 用于开关电路、充-放电电路或其他瞬间电流电路时，建议降至30%以下，串联一只电阻器，将电流限制在300 mA 以下。 当环境温度t超过85℃时，建议工作电压不要超过图1所示的范围。 2 纹波电流与纹波电压 2.1 纹波电流 若施加在钽电容器上的纹波电流Im…     

基于薄外延技术的高压BCD兼容工艺

针对高压应用领域,开发了一种基于薄外延技术的高压BCD兼容工艺,实现了900V高压双RESURF LDMOS与低压CMOS,BJT器件的单片集成.与传统厚外延技术相比,工艺中n型外延层的厚度减小为9μm,因此形成pn结对通隔离的扩散处理时间被极大减小,结隔离有更小的横向扩散,节约了芯片面积,并改善了工艺的兼容性.应用此单层多晶、单层金属高压BCD兼容工艺,成功研制出一种基于耦合式电平位移结构的高压半桥栅极驱动电路,电路高端浮动偏置电压为880V.     

基于薄外延技术的高压BCD兼容工艺

针对高压应用领域,开发了一种基于薄外延技术的高压BCD兼容工艺,实现了900V高压双RESURF LDMOS与低压CMOS,BJT器件的单片集成.与传统厚外延技术相比,工艺中n型外延层的厚度减小为9μm,因此形成pn结对通隔离的扩散处理时间被极大减小,结隔离有更小的横向扩散,节约了芯片面积,并改善了工艺的兼容性.应用此单层多晶、单层金属高压BCD兼容工艺,成功研制出一种基于耦合式电平位移结构的高压半桥栅极驱动电路,电路高端浮动偏置电压为880V.     

深硅槽开挖工艺

本文介绍了硅槽应用,即硅槽隔离和硅槽电容,对器件性能的改善。并介绍了硅槽隔离和硅槽电容的形成步骤及硅槽刻蚀剖面的形貌控制,CBrF_3刻蚀硅槽侧壁保护层的形成等等。