跨导线性原理及应用研究

跨导线性电路是电流模式电路中应用非常广泛的电路形式,可以用于分析和构造很多实用的电路。文中介绍了跨导线性的基本原理,给出了几种用双极型晶体管和MOS管实现的跨导线性电路形式。最后给出了跨导线性电路在电流模式电路中的应用实例。     

Modeling of mismatch effect in submicron MOSFETs based on BSIM3model and parametric tests

Mismatch between identically designed MOS transistors plays an important role in the performance of analog circuits. This paper reports a MOS transistor mismatch model applicable for submicron CMOS technology and developed based on the industry standard BSIM3v3 model. A quick way to estimate drain current mismatch based on parametric test data was also suggested     

CMOS analog divider and four-quadrant multiplier using poolcircuits

CMOS divider and four-quadrant multiplier circuits using the pool circuits are presented. Using CMOS differential amplifiers and MOS transistors biased in the saturation region, the new analog divider and multiplier are presented. Experimental and simulation results are given-to verify the theoretical analyses. The proposed circuits are expected to be useful in analog signal processing applications     

Very low-voltage analog signal processing based on quasi-floating gate transistors

A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.     

Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X–Y Zoning Method: Case Study

We propose a method of diagnosing analog circuits that is achieved by combining an operation-region model and an X–Y zoning method. The X–Y zoning method can be used to detect faults in analog circuits by using the relationship between circuit inputs and outputs. The operation-region model can be used to analyze/model circuit behaviors by utilizing changes in the operation regions of MOS transistors in a circuit. Operation regions are obtained from transistor node voltages at sampling time corresponding to a particular excitation of the input value and the corresponding output value. Since we developed a data processing method to handle data discretely, we could implement a procedure for diagnosis based on the preset test, which is a method of diagnosing digital circuits. We demonstrated the effectiveness of our method by applying it to ITC’97 benchmark circuits with hard and soft faults. We found that the diagnostic resolution is one for every fault.     

MOS-only second order current-mode LP/BP filter

In this study, a current-mode dual output low-pass and band-pass filter is presented using only six MOSFET transistors in its core. Transconductances and gate-to-source capacitances of the MOS transistors are employed instead of passive resistors and capacitors. The proposed circuit exhibits important features such as simplicity, low-voltage/power operation, reduced chip area and wide frequency range compared to classical analog circuits that require active elements with large number of transistors. Simulations are performed to verify the theoretical results.     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

模电教学中BJT与MOS的近似性分析

BJT 与MOS器件及电路是模电重要内容；教学中二者的电路模型与分析方法不一致，学生困惑于两套不同的器件及电路知识。本文在遵循器件及电路工作原理的基础上，首次将二者在小信号模型、电路参数、I-V方程、特性曲线、工作区间、指标计算上进行完整的近似性分析及一致性推导；在二者电路计算中，用三种单管单级放大器实例，阐述近似分析方法的便利性。本文是模电教学的有力补充。     

A monolithic 200-V CMOS analog switch

A new high-voltage CMOS technology is described which can increase the operating voltage of these circuits to more than 200 V. This represents approximately an order of magnitude improvement over present-day commercially available CMOS devices. The technology is straightforward to implement and uses n-channel MOS transistors and high-voltage p-channel devices. As an example of the capability of the technology, a monolithic quad CMOS analog switch has been fabricated which can handle 200-V, 0.3-A analog signals, with a dynamic range in excess of 150 dB.     

A comprehensive submicrometer MOST delay model and its applicationto CMOS buffers

In this paper, an accurate delay model for MOS transistors in submicrometer CMOS digital circuits is presented. It takes into account a ramp shape input voltage and a feedforward capacitive coupling between gate and drain nodes, along with the main second-order effects present in short-channel MOS transistors. The proposed model shows an average agreement with SPICE simulations of 3% in the calculation of the propagation time, tested on a minimum inverter with a 0.7-μm CMOS reference technology for a wide range of input voltage slopes. An example of application in optimization algorithms regarding CMOS tapered buffers is also reported. A maximum error ranging from 3-6% with respect to SPICE has been found for the optimized circuits     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Silicon-on-insulator approach for power IC's integrating verticalDMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions     

MOS-bipolar monolithic integrated circuit technology

A technique for the fabrication of p-channel MOS transistors and bipolar transistors within monolithic integrated circuits is described. Total process compatibility has been achieved without compromising either the n-p-n bipolar or p-channel MOS characteristics. The technology developed is similar to that used for conventional integrated circuits until the channel oxidation step, A low temperature oxidation followed by a high temperature anneal process that produces negligible changes in preceding diffusion profiles was used to form this oxide. Bias temperature tests of MOS capacitors have shown the oxide to be reproducibly free of contamination. A high slew rate MOS bipolar operational amplifier has been designed and fabricated on 0.045- by 0.045-in chip using the new technology. Typical characteristics are slew rate =80 V/µs voltage gain = 70 dB. The MOS transistors are used as active loads and level shifters in this circuit and provide a much improved frequency response over conventional circuits using p-n-p lateral transistors.     

Microwave CMOS-device physics and design

This paper discusses design issues and the microwave properties of CMOS devices. A qualitative understanding of the microwave characteristics of MOS transistors is provided. The paper is directed toward helping analog IC circuit designers create better front end radio-frequency CMOS circuits. The network properties of CMOS devices, the frequency response, and the microwave noise properties are reviewed, and a summary of the microwave scaling rules is presented     

DTMOS Technique for Low-Voltage Analog Circuits

In this paper, the application of dynamic threshold MOS (DTMOS) technique for low-voltage analog circuits is explored. The body terminal of PMOS transistors in bulk CMOS technology can be used as the forth terminal to enhance the performance of low-voltage analog circuits. To show the effectiveness of this technique, we have designed a continuous time common mode feedback (CMFB) circuit for a sub 1-V opamp and a new sub 1-V, 1-bit quantizer. A 0.8-V opamp with embedded CMFB and a 0.8-V, 1-bit quantizer for low-voltage DeltaSigma modulators are implemented in 0.18-mum CMOS technology. The simulation results as well as the measurement data of these blocks are presented in this paper     

A novel two-dimensional MOS transistor for analog applications

In analog MOS integrated circuits, matching between transistors is a critical requirement because the circuit performance is determined by the device matching available. A new type of matched configuration is presented in this paper which utilizes the inherent 2-D geometry of an MOS transistor which was hitherto unexplored. This has been achieved by adding two more diffusion regions along the length of a normal MOS transistor. The characteristics of the device thus formed have been modeled in the linear region for different configurations, by solving the 2-D current continuity equation. For the saturation region, an empirical relation has been given. Theoretical and experimental results for a test chip have been presented. A few potential applications are mentioned.     

A method for the measurement of the turn-on condition in MOS transistors

Metal-oxide-silicon (MOS) integrated circuits usually consist of MOS transistors and interconnections. Both, interconnections and MOS transistors are built up of diffused regions in the bulk substrate and conductive strips (metal or polycrystalline silicon) on top of the oxide. For proper electrical operation the interconnection paths should not exhibit MOS transistor effects, i.e. should not induce inversion layers at the silicon-silicon dioxide interface. Furthermore from a designer's point of view it will be desired that some transistors operate in the saturated mode and others in the non-saturated mode. This implies that a method for the determination of the turn-on of channel conduction is highly desirable for designers of MOS integrated circuits. Using a straightforward definition of turn-on, a fast and simple measurement method will be presented for the determination of the relation between gate voltage and diffused region voltage for MOST structures in the turn-on condition.     

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%     

Experimental Evaluation of Reliability of Deep Submicron SOI MOS Transistors at High Temperatures

In this paper, 0.18–0.5 μm SOI MOS transistors are tested for compliance with the reliability criteria applied to high-temperature electronics and their components. The main parameters of SOI MOS transistors are measured in the temperature range from ?60 to +300°С. The specific behavior exhibited by SOI MOS transistors at high temperatures should be taken into account when designing high-temperature integrated circuits so as to avoid premature failures and increase the reliability of devices.