一种改进输入时钟的EEPROM电荷泵设计

介绍了RFID无源电子标签中EEPROM的基本结构与工作原理。分析了NMOS管Dickson电荷泵及其由NMOS管构成的栅压自举电荷泵的特点与不足。针对当前电荷泵存在的电荷倒流、体效应问题,设计了一种改进输入时钟的电荷泵电路。通过对比仿真后发现,改进设计的电荷泵能减少电荷倒流、提高传输效率。已成功应用于RFID芯片的EEPROM中。     

一种CMOS电荷泵电路的设计

本文采用SMIC 0.18m CMOS工艺分析设计了一种CMOS电荷泵电路,电路采用PMOS与NMOS构成的互补CMOS开关,有效地减小了电流失配、电荷泄漏、开关效应等电荷泵的非理想效应。仿真结果现实,在1.8V电源电压条件下,输出电压线性度良好,电荷泵电路的静态功耗仅为1.44m W;电荷泵上拉和下拉电流变化较小,电流失配率约为1.3%。     

一种用于LCD驱动的高效电荷泵的设计

电荷泵是一种流行的获取高于供电电源的直流电压转换技术.传统的电荷泵电路采用二极管连接的NMOS管级联来获取较高的电压,由于阈值电压的作用,这种电荷泵的提升效率会随着级数的增加而下降.为了提高效率,文中提出了一种提升5倍电压的采用液晶显示器(LCD)驱动的新型电荷泵结构.特别设计了开关管的栅控电路,消除了阈值电压对电压提升效率的影响,并且通过对开关管尺寸和控制时钟的进一步优化,提高了电压转换效率,降低了功耗,特别适合于小尺寸LCD驱动的需要.     

一种消除阈值电压影响的高效率电荷泵

提出了一种基于Dickson电荷泵结构的片上升压电路,由两相非交叠时钟驱动,并与电平转换单元配合使用.该电路将最后一级的传输管NMOS管替换为PMOS管,再由电平转换单元产生的电压来控制该PMOS管的栅端电压,使之在导通时彻底打开,从而消除该级的阈值电压损失,提高了输出电压.     

应用于PLL的改进型自校准CMOS电荷泵电路

为提高锁相环中自校准电荷泵电路的稳定性,提出了一种改进型宽摆幅自校准CMOS电荷泵电路.该电路通过引入宽摆幅自校准反馈回路,使电荷泵在输出电压变化范围较大时,UP/DOWN两个开关电流完全匹配,而且该电路不需要专门的频率补偿即可确保绝对稳定.该电荷泵采用0.25μm CMOS混合信号工艺实现.当供电电压2.5V,电荷泵输出节点电压在0.3~2.2V范围内变化时,UP和DOWN电流差值小于2%.     

一种应用于反熔丝FPGA的电荷泵电路

电荷泵（Charge Pump）电路以其可成倍输出自身输入电压的特性而被广泛应用于各种芯片的驱动电路中。在反熔丝FPGA中,反熔丝为高压一次编程器件,在编程过程中需要通过高压隔离管将反熔丝与其它器件隔离开,而高压隔离管在工作时需要大于芯片电源VCCA的电压来驱动,如何提供高压保证隔离管能够无损传输数据是反熔丝FPGA研发时必须要考虑的问题。本文提出了一种应用于反熔丝FPGA的电荷泵电路,电路具有快速启动的特点,同时电路工作频率可调,通过在电路中增加冗余NMOS结构,提高了电路在工作中的安全性,该电路在工作时能保证熔丝编程过程中除了反熔丝以外的其他器件不受编程电压的影响,且在编程结束后通过电荷泵输出电压打开隔离管完成信号的无损传输,能够满足反熔丝FPGA对于电荷泵的需求。     

应用于Flash存储器的一种高效低纹波电荷泵设计

针对交叉耦合型电荷泵电荷回流的问题,本文提出了一种新型六相位电荷泵结构,电荷泵的主体由3个NMOS管和3个泵电容组成。考虑到时钟驱动能力对电荷泵性能的影响,设计通过增加额外的时钟驱动模块实现四相位到六相位的时钟转换,从而减小电荷泵的上升时间并改善输出电压。此外,电路采用并联双支路结构减小输出电容的充放电时间间隔,以减小输出纹波。基于0.13μm工艺的仿真结果表明,在时钟频率为20MHz,负载电容为50pF,负载电流为300μA的条件下,该电路可以实现3.3V到15V的电压转换,效率可达到67.7%,输出纹波仅为38.5mV。     

低功耗电荷泵可编程增益放大器的设计与实现

提出了一种低功耗电荷泵可编程增益放大器(PGA)电路模型.通过简单数学建模和VerilogA仿真,得出了一般自动增益控制电路(AGC)优化稳定时间的条件和简化模型,通过ADC、电荷泵,进一步简化电路,降低功耗,并实现数字控制功能.根据这种设计,采用TSMC 0.18 μm CMOS 单层多晶硅6层金属工艺,实现了一个功耗电流为1 mA、线性增益范围为60 dB的电荷泵可编程增益放大器.     

一种带自适应电荷泵的超低功耗NMOS LDO

设计了一种带自适应电荷泵的超低功耗快速瞬态响应NMOS LDO,电路主要包含误差放大器、缓冲器、功率级、动态零点模块以及自适应电荷泵模块。该自适应电荷泵能够根据负载电流的大小调节工作频率,在兼顾大负载条件下功率管栅极需求的同时,保证了轻载下超低功耗的需求。同时为了满足电路中快速瞬态响应的需要,加入了动态电流电路。电路基于0.18μm BCD工艺设计,其工作电压范围为2.5～3.6 V,输出电压为1.2 V,负载范围为10μA～20 mA,工作的温度范围为-40～125℃。仿真结果显示,所设计的LDO供电电压调整率可达到1.123 mV/V,重载跳轻载时的恢复时间和轻载跳重载时的恢复时间分别为260μs和5μs,而静态电流最小仅为0.291μA。     

一种快速升压的片上电荷泵电路设计

设计了一种快速升压的片上电荷泵电路,该电路由时钟产生电路和电荷泵核组成。电荷泵核基于传统Dickson电荷结构,在前四级引入预充管,增加节点初始电压,提高电荷泵升压速度,时钟产生电路能产生占空比约为30%的稳定时钟信号,用它驱动电荷泵核可以减小充放电流失配等问题,进一步提高电荷泵升压速度。基于华虹NEC 0.35μs CMOS工艺,HSPICE仿真结果显示：在5V电源电压下,电荷泵仅需要57.625μs就可以从0V升压到20V,比传统的MOS管Dickson电荷泵快了20.055μs。     

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and I_Q of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.     

变频和脉冲跳变双模式控制电荷泵的建模和实现

提出了一种高性能电荷泵的建模和设计实现方法.为了实现在大的负载电流变化范围内具有高转换效率和低输出电压纹波,提出了变频模式(VFM)和脉冲跳变模式(PSM)双模式控制的电荷泵,并建立了相应的数学模型以方便设计参数的分析和选取.芯片采用TSMC0.35 μm标准CMOS数模混合工艺进行设计制造,总面积约为1.4 mm×1.5 mm.测试结果表明,所设计的电荷泵在全负载电流范围内(5 ～ 100 mA)能够实现双模式的自动切换,取得较低电压纹波和较高效率,达到了设计预期,从而验证了变频和脉冲跳变双模式控制电荷泵的可行性.     

一种新的SOI射频集成电路结构与工艺

立足于与常规CMOS兼容的SOI工艺，提出了电子束／I线混合光刻制造SOI射频集成电路的集成结构和工艺方案。该方案只使用9块掩模版即完成了LDMOS、NMOS、电感、电容和电阻等元件的集成。经过对LDMOS、NMOS的工艺、器件的数值模拟和体硅衬底电感的初步实验，获得了良好的有源和无源器件特性，证明这一简洁的集成工艺方案是可行的。     

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are examined. The radiation tests are performed at ⁶⁰Co sources at the dose rate of 50 rad (Si)/s. The investigation''s results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation structure is the main total dose problem. The total ionizing dose (TID) radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is established. The I-V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I-V characteristics of 180 nm commercial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

应变Si NMOS器件总剂量辐射对单粒子效应的影响

针对应变Si NMOS器件总剂量辐射对单粒子效应的影响机制,采用计算机TCAD仿真进行研究。通过对比实验结果,构建50 nm应变Si NMOS器件的TCAD仿真模型,并使用该模型研究处于截至态(V_ds=1 V)的NMOS器件在总剂量条件下的单粒子效应。实验结果表明,总剂量辐照引入的氧化层陷阱正电荷使得体区电势升高,加剧了NMOS器件的单粒子效应。在2 kGy总剂量辐照下,漏极瞬态电流增加4.88%,而漏极收集电荷增量高达29.15%,表明总剂量辐射对单粒子效应的影响主要体现在漏极收集电荷的大幅增加方面。     

一种高速低过冲电荷泵电路的设计

为了有效降低传统电荷泵电路的充放电过冲电流,提高电荷泵输出控制电压的稳定性,提出、设计并实现了一种高速低过冲的电荷泵结构,该电路适用于高速锁相环及时钟数据恢复电路.电路在电源电压为1.2 V的0.13 μm CMOS工艺下设计实现,并对版图数据进行了HSPICE模拟,其结果表明,电路在2.5 GHz的速度下能很好的工作,同时电流过冲相比传统电荷泵下降了70%.     

Substrate noise isolation improvement in a single-well standard CMOS process

This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well proposed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.     

用于锁相环的低失配CMOS电荷泵设计

设计了一种用于锁相环的低失配CMOS电荷泵电路,采用互补差分输入。互补差分管的使用有效地解决了电荷泵的时钟馈通和电荷注入等非理想现象。同时,利用自举的方法消除了电荷共享现象。在电路和版图的设计中,充分考虑了对称性对电流失配的影响。本电荷泵电路基于新加坡Chartered0.25μmN阱CMOS工艺实现,采用Candence中的Spectre仿真工具进行仿真,电源电压为3.3V。测试结果表明,在本芯片需要的各种电荷泵电流下其失配都低于0.65%。本电荷泵电路已应用于射频调谐器当中。