A new CMOS class AB serial link transmitter with a low supply voltage sensitivity

This paper presents a new class AB transmitter with a low supply voltage/ground bouncing sensitivity for 10 Gb/s serial links. The low sensitivity of the output current to supply voltage fluctuation and ground bouncing is achieved by operating the system in a rail-to-rail swing mode. High data rates are obtained by multiplexing at low-impedance nodes and inductive shunt peaking with active inductors. The fully differential configuration and bipolar signaling of the transmitter minimize the effect of both common-mode disturbances and electro-magnetic interferences exerted from channels to neighboring devices. The class AB operation of the transmitter minimizes its static power consumption. The proposed transmitter is implemented in a 1.2 V 0.13μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Both pre and post-layout simulation results demonstrate that the transmitter conveys a sufficiently large differential output current that is insensitive to supply voltage fluctuation and ground bouncing at 10 Gb/s. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the M.A.Sc. degree in chemical engineering, and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Ontario, Canada, and Lambton College of Applied Arts and Technology, Sarnia, Ontario, Canada. He was with Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer during 1989–1994. Since 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with Ajoy Opal). Dr. Yuan received the Ryerson Research Chair award from Ryerson University in Jan. 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 1997–1998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. Dr. Yuan is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Minghai Li received the B.Eng. (96) and M.A.Sc (06) degrees from North University of China and Ryerson University, Toronto, Ontario, Canada, respectively, both in Electrical and Computer Engineering. During 1996–2001, he was with Motorola Semiconductor (China) as a MCU product engineer. He was involved with MCU new product design, simulation, and test program development. He was a research assistant and a M.A.Sc student with the Microsystems Research Laboratory in the Department of Electrical and Computer Engineering at Ryerson University. He is now with Micron Technology Inc., Boise, Idaho, USA as a design engineer. His research interest is in the design of CMOS mixed-signal circuits for high-speed data transmission, including multiplexer, driver, pre-emphasis, and VCOs.     

Novel Architectures of Class AB CMOS Mirrors with Programmable Gain

Two schemes for power-efficient gain-programmable V-I conversion based on class AB CMOS mirrors are introduced. The proposed topologies also allow for high-speed gain-programmable precision rectification. Experimental results from a test chip prototype in 0.5- m CMOS technology with ±1 V supplies are shown that validate the proposed circuits.     

A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links

This paper presents an in-depth study of the pros and cons of voltage-mode multiplexers for Gbps serial links and exploits the advantages of multiplexing in current domain. In addition, it proposes a new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by multiplexing at a low-impedance node. Multiplexing speed is further improved by inductive shunt peaking with active inductors. The differential configuration of the multiplexer minimizes the effect of common-mode disturbances, particularly those coupled from the power and ground rails. The flow of the output currents in the opposite directions minimizes the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed-circuit-board (PCB) traces. The proposed multiplexer draws a constant current from the supply voltage, thereby minimizing both switching noise and noise injected to the substrate. A fully differential CMOS current-mode 8-to-l multiplexer has been implemented in TSMC’s 1.8 V 0.18 μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye-opening when multiplexed at 10 Gbps.Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. Since 2002, she has been a research assistant with the System-on-Chip research lab of Ryerson University. She is currently a M.A.Sc candidate under the supervision of Dr. Fei Yuan in the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada. Her research interests are in analog CMOS circuit design for high-speed data communications. She was awarded the Ontario Graduate Scholarship (OGS) in 2003–2005 for academic excellence.Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering and PhD. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively.During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching” award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

Winner-Take-All Class AB Input Stage

A novel technique to implement class AB differential amplifier input stages is proposed. It is based on the use of Winner-Take-All circuits for achieving dynamic current boosting, and is well suited for low-voltage operation. Experimental measurements of an OTA using this technique, fabricated in a 0.5-μm CMOS technology, show a slew rate of 92 V/μs for an 80-pF load and 120 μW of static power consumption.     

10Gb/s误码议的设计与研制

介绍了采用多功能的CDR芯片和单片机设计操作简捷、功能强大、成本低廉的10Gb/s误码议的方案,使用该设计方案的误码议已制作出样机,并应用于XFP光模块的灵敏度测试中,对光模块灵敏度准确性的提高和生产成本的降低具有重要意义.     

一种 65纳米 CMOS 10–20 Gb/s PAM2-4接收和发送端

本文提出了65纳米CMOS工艺下的一种 10Gb/s PAM2, 20Gb/s PAM4高速低功耗的有线电互连发送和接收端。发送端面积为430μm × 240μm,功耗为 50.56mW。通过集成可编程的 5阶预加重均衡器,发送端可以在宽范围区间内补偿各种不同的信道损失,并且针对信道特点的不同采用相应的发送电压幅度从而降低信号发送功耗。接收端均衡器面积为146μm × 186μm,功耗为5.3mW。     

A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430×240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146×186 μm2 and consumes 5.3 mW power.     

低功耗10Gb/s CMOS 1:4分接器

采用TSMC0．18μmCMOS工艺实现了一个应用于光纤通信系统SDHSTM-64的10Gb／s 1：4分接器,整个系统采用树型结构,由一个高速1：2分接单元,两个低速1：2分接单元。分频器,数据及时钟输入输出缓冲组成,其中高速分接单元采用共栅结构,单时钟输入的触发器实现;而低速分接单元则由动态CMOS逻辑实现,两个基本结构的使用都有利于降低功耗。该芯片工作速度最高达12．5Gb／s。功耗仅为120mW。     

基于受激布里渊散射的40 Gb/s时钟提取试验

对基于受激布里渊散射效应(SBS)的时钟恢复系统模型进行了试验验证,实现了40 Gb/s载波抑止归零码(CSRZ)的全光时钟提取.试验结果表明由于产生了强烈的受激布里渊散射的梳状放大特性,光信号的时钟分量得到显著增强.在不改变该模型结构的基础上,利用G.652普通单模光纤传输8 km而不经过色散补偿的40 Gb/s载波抑止归零码光信号恶化以后仍可进行良好地时钟恢复,时钟抖动小于6.5 ps.研究证明该方案可在一定程度上抵制传输信号恶化所造成的影响,并无明显的码型效应,适合高速长距离全光时钟提取.     

A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186μm^2 and consumes 5.3 mW power.     

2.5Gb/s和3.125Gb/s速率级0.35μmCMOS限幅放大器

采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p，单端输出摆幅为400mVp-p，功耗250mW，含信号丢失检测功能，可以满足商用化光纤通信系统的使用标准。     

10 Gb/s 0.18 μm CMOS时钟恢复芯片

介绍了基于0．18μmCMOS工艺的10Gb／s时钟恢复电路的设计。核心电路采用预处理加简单锁相环的结构。模拟结果表明，该电路能工作在10GHz频率上，输入信号峰值0．4V时，同步范围可以达到270MHz，总功耗210mW。     

10Gb/s0.18μm CMOS工艺复接器设计

介绍一种超高速4∶1复接器集成电路。电路采用0.18μm CMOS工艺实现,供电电源1.8 V。电路采用源极耦合场效应管逻辑(SCFL),与静态CMOS逻辑相比具有更高的速度。为了避免高速时序电路中常见的时钟偏差,在时钟树中放置了缓冲器。在设计中采用有源电感的并联峰化技术有效地提高了电路的工作速度。仿真结果表明电路工作速度可达10 Gb/s,复接器芯片面积约为970×880μm2。     

10 Gb/ s 0. 18 􀀁m CMOS 激光二极管驱动器芯片

基于0．18μm CMOS工艺设计的10Gb／s激光二极管驱动器电路。核心单元为两级直接耦合的差分放大器，电路中采用了并联峰化技术和放大级直接耦合技术以扩展带宽，降低功耗。模拟结果表明，在1．8V电源电压作用下该电路可工作在10Gb／s速率上，输入单端峰峰值为0．3V的差分信号时，在单端50Ω负载上的输出电压摆幅可达到1．4V，电路功耗约为85mW。     

一种用于10 Gb/s Serdes的40 nm CMOS锁相环

提出了一种应用于10 Gb/s高速串并接口电路(Serdes)的高性能锁相环。采用正交压控振荡器(QVCO)实现4路等相位间隔的5 GHz时钟,输出采用2分频单转差缓冲器,实现可忽略相差的8路等相位间隔的2.5 GHz时钟。电荷泵中采用负反馈技术,以提高电流匹配性能。在SMIC 40 nm工艺下完成设计,在 1.1 V的供电电压下,锁相环的总电流为7.6 mA,输出5 GHz时钟在10 kHz~100 MHz积分范围内的均方根抖动约为107 fs,芯片尺寸仅为780 μm×410 μm。     

Design of Two‐Stage Class AB CMOS Buffers: A Systematic Approach

A systematic approach for the design of two‐stage class AB CMOS unity‐gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity‐gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 µm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 µW).     

Cost‐Effective Transition to 40 Gb/s Line Rate Using the Existing 10 Gb/s‐Based DWDM Infrastructure

In this paper, we propose and demonstrate a cost‐effective technique to upgrade the capacity of dense wavelength division multiplexing (DWDM) networks to a 40 Gb/s line rate using the existing 10 Gb/s‐based infrastructure. To accommodate 40 Gb/s over the link optimized for 10 Gb/s, we propose applying a combination of super‐FEC, carrier‐suppressed return‐to‐zero, and pre‐emphasis to the 40 Gb/s transponder. The transmission of 40 Gb/s DWDM channels over existing 10 Gb/s line‐rate long‐haul DWDM links, including 40×40 Gb/s transmission over KT's standard single‐mode fiber optimized for 10 Gb/s achieves successful results. The proposed upgrading technique allows the Q‐value margin for a 40 Gb/s line rate to be compatible with that of 10 Gb/s.     

A Study of Different Class AB Log Domain First Order Filters

Several different class AB log-domain/translinear filters are compared in terms of their noise and distortion behavior using both analytical and simulation results. A few of the circuit topologies shown have not been considered before and are derived using a new theory for class AB dynamical circuits recently proposed. The study, although approximate, suggests ways in which both noise and distortion performance may be optimized by appropriate choice of circuit topology. Other practical aspects of the designs are also discussed.     

可达到40Gb/s的材料选择:SiGe与GaAs和InP的比较

对可达到 2 .5～ 40 Gb/s数据速率的 Si Ge与 Ga As和 In P材料进行了比较 ,还对各种材料和工艺的典型特征进行了分析     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。