共查询到20条相似文献,搜索用时 11 毫秒
1.
The trapping/detrapping behavior of charge carriers in ultrathin SiO2/TiO2 stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO2 films at low temperature (<200 °C) on strained-Si/relaxed-Si0.8Ge0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO2/TiO2 stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO2 layer. The increase in the gate current density observed during CVS from room temperature up to 125 oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10−19 cm2 as compared to 10−16 cm2 in SiO2 has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed. 相似文献
2.
Isodiana Crupi 《Microelectronic Engineering》2009,86(1):1-3
Charge trapping and trap generation in field-effect transistors with SiO2/HfO2/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case. 相似文献
3.
D. Spassov 《Microelectronic Engineering》2008,85(1):214-222
The influence of the rapid thermal annealing (RTA) in vacuum at 1000 °C on the leakage current characteristics and conduction mechanisms in thermal Ta2O5 (7-40 nm) on Si has been studied. It was established that the effect of RTA depends on both the initial parameters of the films (defined by the oxidation temperature and film thickness) and annealing time (15-60 s). The RTA tends to change the distribution and the density of the traps in stack, and this reflects on the dielectric and leakage properties. The thinner the film and the poorer the oxidation, the more susceptible the layer to heating. The short (15 s) annealing is effective in improving the leakage characteristics of poorly oxidized samples. The RTA effect, however, is rather deleterious than beneficial, for the thinner layers with good oxygen stoichiometry. RTA modifies the conduction mechanism of Ta2O5 films only in the high-field region. The annealing time has strong impact on the appearance of a certain type of reactions upon annealing resulting to variation of the ratio between donors and traps into Ta2O5, causing different degree of compensation, and consequently to domination of one of the two mechanisms at high fields (Schottky emission or Poole-Frenkel effect). Trends associated with simultaneous action of annealing and generation of traps during RTA processing, and respectively the domination of one of them, are discussed. 相似文献
4.
C. Martínez-DomingoX. Saura A. CondeD. Jiménez E. MirandaJ.M. Rafí F. CampabadalJ. Suñé 《Microelectronic Engineering》2011,88(7):1380-1383
Multiple successive breakdown events are reported for HfO2/Al2O3 nanolaminate dielectrics grown by atomic-layer deposition. The first breakdown distribution is not a Weibull distribution and shows a long TBD tail at high failure percentiles. Analysis of the correlation between time-to-breakdown and initial current leakage allows identifying this tail with extrinsic breakdown. Screening of the data to eliminate the extrinsic tail demonstrates that the successive breakdown events are completely uncorrelated and perfectly match the successive breakdown theory. The statistical correlation between initial current and extrinsic breakdown distribution is explained in terms of variations of the unintentional interfacial SiOx layer at the silicon substrate/dielectric interface. 相似文献
5.
Zong-Hao YeKuei-Shu Chang-Liao Feng-Wen ShiuTien-Ko Wang 《Microelectronic Engineering》2011,88(7):1194-1197
Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al2O3 as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al2O3/high-k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al2O3 as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al2O3/high-k stacked blocking layer approaches, retention property can be further improved. 相似文献
6.
A. Molle S. Spiga M.N.K. Bhuiyan G. Tallarida M. Perego C. Wiemer M. Fanciulli 《Materials Science in Semiconductor Processing》2008,11(5-6):236
The atomic oxygen-assisted molecular beam deposition of Gd2O3 films on Ge(0 0 1) substrates has been performed at various growth temperatures. The compositional aspects, the interface details and the surface structure have been investigated by in situ X-ray photoelectron spectroscopy, time-of-flight secondary ion mass spectroscopy and in situ atomic force microscopy, and ex situ. The interface layer of GeO2 has been subsequently fabricated by means of atomic oxygen exposure in order to passivate the high-k/Ge interface. The electrical characterization on the final Gd2O3/GeO2/Ge structure has been reported. The electrical characterization on the Al gate/Gd2O3/GeO2/Ge structure exhibits a MOS behavior, indicating the beneficial effect of GeO2 passivation. 相似文献
7.
Haigui Yang Masatoshi Iyota Shogo Ikeura Dong Wang Hiroshi Nakashima 《Solid-state electronics》2011,60(1):128-133
A method of Al2O3 deposition and subsequent post-deposition annealing (Al2O3-PDA) was proposed to passivate electrically active defects in Ge-rich SiGe-on-insulator (SGOI) substrates, which were fabricated using Ge condensation by dry oxidation. The effect of Al2O3-PDA on defect passivation was clarified by surface analysis and electrical evaluation. It was found that Al2O3-PDA could not only suppress the surface reaction during Al-PDA in our previous work [Yang H, Wang D, Nakashima H, Hirayama K, Kojima S, Ikeura S. Defect control by Al-deposition and the subsequent post-annealing for SiGe-on-insulator substrates with different Ge fractions. Thin Solid Films 2010; 518: 2342-5.], but could also effectively passivate p-type defects generated during Ge condensation. The concentration in the range of 1016-1018 cm−3 for defect-induced acceptors and holes in Ge-rich SGOI drastically decreased after Al2O3-PDA. As a result of defect passivation, the electrical characteristics of both back-gate p-channel and n-channel metal-oxide-semiconductor field-effect transistors fabricated on Ge-rich SGOI were greatly improved after Al2O3-PDA. 相似文献
8.
Rakesh Sohal Mohamed Torche Karsten Henkel Patrick Hoffmann Massimo Tallarida Dieter Schmeißer 《Materials Science in Semiconductor Processing》2006,9(6):945
We elaborate the possibility of combining high-k dielectrics with wide band gap semiconductors, i.e. Pr2O3 on SiC. The thermal stability of interfacial aluminum oxynitride (AlON) layers between Pr-oxide and SiC has been investigated by synchrotron radiation photoemission spectroscopy (SRPES). The interface of Pr2O3 with SiC is reactive. Such reaction is successfully prevented by utilizing a stable interlayer derived from AlON. No elemental carbon is observed in detectable amount after Pr-Oxide deposition on AlON covered 3C-SiC and subsequent vacuum annealing. After vacuum annealing at 500 °C AlON transformed to AlN and Pr-aluminate with a small amount of CN close to the SiC surface which were thermally stable even at 900 °C. AlON hence provides a good diffusion barrier between Pr-oxide dielectric and 3C-SiC. 相似文献
9.
D. Kitayama T. KoyanagiK. Kakushima P. AhmetK. Tsutsui A. NishiyamaN. Sugii K. NatoriT. Hattori H. Iwai 《Microelectronic Engineering》2011,88(7):1330-1333
The effect of a thin Si layer insertion at W/La2O3 interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La2O3 layer by forming an amorphous La-silicate layer at the W/La2O3 interface. In addition, positive shifts in Vfb and Vth caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La2O3 dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high Eeff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit. 相似文献
10.
GaAs metal–oxide–semiconductor(MOS) capacitors with HfTiO as the gate dielectric and Al2O3 or ZnO as the interface passivation layer(IPL) are fabricated. X-ray photoelectron spectroscopy reveals that the Al2O3 IPL is more effective in suppressing the formation of native oxides and As diffusion than the ZnO IPL. Consequently, experimental results show that the device with Al2O3 IPL exhibits better interfacial and electrical properties than the device with ZnO IPL: lower interface-state density(7.21012 eV1cm2/, lower leakage current density(3.60107A/cm2 at Vg D1 V) and good C–V behavior. 相似文献
11.
Sung-Yong Chang Myeong-Il Jeong S.V. Jagadeesh Chandra Yong-Boo Lee Hyo-Bong Hong V. Rajagopal Reddy Chel-Jong Choi 《Materials Science in Semiconductor Processing》2008,11(4):122-125
We fabricated a high-k Er-silicate gate dielectric using interfacial reaction between Er and SiO2 films and investigated its thermal stability. The reduced capacitance with increasing annealing temperature is associated with the chemical bonding change of Er-silicate from Er-rich to Si-rich, induced by a reaction between Er-silicate and Si during thermal treatment. Further an increase in the annealing temperature (>500 °C) causes the formation of Si dangling bonds, which is responsible for an increased interface trap density. 相似文献
12.
M.A. PampillónP.C. Feijoo E. San Andrés M. Toledano-LuqueA. del Prado A.J. BlázquezM.L. Lucía 《Microelectronic Engineering》2011,88(7):1357-1360
Amorphous Gd2O3 and Sc2O3 thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiOx growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O2 atmosphere. For post-processing interfacial SiOx thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO2 interface thickness without severely compromising gate dielectric leakage. 相似文献
13.
We report thin-film moisture barriers based on Al2O3/ZrO2 nanolaminates grown by ALD for an encapsulation of OLEDs. In order to optimize the moisture-barrier performance of the nanolaminates, the most important factors affecting the performance were sought by measuring WVTR of the nanolaminates via an electrical Ca test. We found out that both the number of interfaces in the nanolaminates and the thickness of ZrO2 in a unit layer were responsible for the performance. By optimizing the nanolaminate structure, the moisture-barrier performance was enhanced up to 350% from a single layer of the same thickness. The WVTR of 30-nm-thick optimized nanolaminate barrier was 2 × 10−4 g/(m2 day) or less at ambient condition. A storage-lifetime measurement of an OLED with a 100-nm-thick encapsulation layer showed that it could exceed 70,000 h if stored at ambient condition. 相似文献
14.
Electrical properties of mixed HfO2-Ta2O5 films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO2 addition to the Ta2O5 is thickness dependent and the thicker layers exhibit advantages over the pure Ta2O5 (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO2 and Ta2O5 mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta2O5-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO2-Ta2O5 stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified. 相似文献
15.
Yung-Hsien Wu Lun-Lun ChenWei-Chia Chen Chia-Chun LinMin-Lin Wu Jia-Rong Wu 《Microelectronic Engineering》2011,88(7):1361-1364
A Ge-stabilized tetragonal ZrO2 (t-ZrO2) film with permittivity (κ) of 36.2 was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO2. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO2 gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH3 plasma, good leakage current of 4.8 × 10−8 A/cm2 at Vg = Vfb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained. 相似文献
16.
I. Mani?E. Atanassova N. Stojadinovi?D. Spassov A. Paskaleva 《Microelectronic Engineering》2011,88(3):305-313
The stress-induced leakage current in Hf-doped Ta2O5 layers (7; 10 nm) under constant voltage stress at gate injection was investigated in order to assess the mechanisms of conduction, the traps involved and the effect of Hf doping. The amount of Hf is found to affect the conduction mechanisms, the temperature dependence of the leakage current and the current response to the stress. A significant leakage current increase is observed only when the stress voltage and/or stress time exceed the corresponding threshold values, where the charge trapping at the pre-existing traps dominates below and defect generation above these threshold values. The energy levels of the traps responsible for the current transport are estimated. The stress effect on dominant conduction mechanisms appears quite weak, and the nature of the traps controlling the current transport before and after the stress seems to be nearly identical. The results indicate that the constant voltage stress affects the pre-existing traps in Hf-doped Ta2O5 and modifies their parameters, but there is no evidence for stress-induced generation of traps with completely new nature different from oxygen-vacancy related defects. 相似文献
17.
L.Q. Zhu Q. Fang G. He M. Liu X.X. Xu L.D. Zhang 《Materials Science in Semiconductor Processing》2006,9(6):1025
Spectroscopic ellipsometry (SE) with photon energy 0.75–6.5 eV at room temperature has been used to derive the optical properties of high-k ZrO2 thin films on Si(1 0 0) substrates prepared by nitrogen-assisted, direct current reactive magnetron sputtering. The Tauc–Lorentz dispersion method was adopted to model the optical dispersion functions of the thin films as a function of annealing temperature. Excellent agreement has been found between the SE fitting results and X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM) and Fourier transform infrared spectroscopy (FTIR) results, indicating that our model adequately described the measured SE data. Optical band gaps (Eg) were also obtained based on the extracted absorption edge. Our results suggest that nitrogen-assisted process can effectively limit the interfacial layer growth in high-k oxides. 相似文献
18.
Youhei Sugimoto Hideto Adachi Keisuke Yamamoto Dong Wang Hideharu Nakashima Hiroshi Nakashima 《Materials Science in Semiconductor Processing》2006,9(6):1031
High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO2/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfOx and SiO2. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfOx/SiO2/Si to HfSixOy/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO2. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO2. 相似文献
19.
H.D.B. Gottlob T. Echtermeyer T. Mollenhauer J.K. Efavi M. Schmidt T. Wahlbrink M.C. Lemme H. Kurz 《Materials Science in Semiconductor Processing》2006,9(6):904
Novel gate stacks with epitaxial gadolinium oxide (Gd2O3) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10–7 A cm–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd2O3 thickness of 3.1 nm yield current densities down to 0.5 A cm−2 at Vg=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd2O3 gate stacks for future material-based scaling of CMOS technology. 相似文献
20.
A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT. 相似文献