An evaluation of fast wafer level test methods for interconnect reliability control

A number of fast wafer level test methods exist for interconnect reliability evaluation. The relative abilities of three such methods to predict the quality and reliability of the interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are compared with package level Median Time to Failure (MTF) results. The Isothermal test method combined with SWEAT-type test structures is shown to be the most suitable combination for interconnect reliability detection and control over very short times.     

A fast wafer-level screening test for VLSI metallization

A method for screening out poor-quality metallizations from VLSI fabrication lines by wafer-level probing is proposed. Theoretical analysis suggests a linear dependence of the metal line conductance on the square of the current density, at thermal equilibrium. The limit to this linearity for ideally perfect metallizations occurs at the metal melting point, at which there is a sudden decrease in the conductance value to zero. In real interconnects, nonidealities such as localized defects or nonuniform surrounding dielectric at isolated points could lead to a deviation of the conductance from ideal expectations. Using this as a diagnostic, a universal methodology for assessing metal quality, independently of the physical parameters of the metal line, is described. Qualitative correlation with electromigration lifetime results is used to validate the method     

Advanced experimental and computational tools for robust evaluation of on-chip interconnect reliability

Two technologies are introduced that, together, provide a platform for robust evaluation of interconnect reliability. One is the DISMAP technology, which provides plots of the displacement and strain fields of cross-sectioned interconnect structures under various loading conditions. Measurements provided by DISMAP reveal how multilevel-interconnect structures interact structurally, for example what type of strain fields exist during thermal cycling. A complimentary technology, known as probabilistic analysis, is also described and applied using the NESSUS software. Probabilistic analysis combines statistical uncertainty with physics-based models to predict the probability of failure and also to reveal the relative importance of the various uncertainties associated with interconnect manufacturing. By comparing the predictions of physical models to DISMAP measurements, the validity of those models are evaluated.     

Cyclic bending reliability of wafer-level chip-scale packages

In this paper, both experimental and numerical studies are conducted to investigate board-level reliability of wafer-level chip-scale packages under four-point cyclic bending conditions that combine different deflection amplitudes and excitation frequencies. In addition to the fatigue lives of the test vehicle, locations and modes of fractured solder joints are observed. In the numerical modeling, inertia forces along with rate-dependent material properties of the solder joints are considered in order to capture frequency-dependent characteristics of this particular test methodology. Through the dynamic finite element analysis, plastic strain energy densities accumulated per bending cycle within the critical solder joint are calculated and together with the experimental results, parameters for the Morrow fatigue model are calibrated.     

A new maximal diagnosis algorithm for interconnect test

Interconnect test for highly integrated environments becomes more important in terms of its test time and a complete diagnosis, as the complexity of the circuit increases. Since the board-level interconnect test is based on boundary scan technology, it takes a long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue. Since the board-level test is performed for repair, noticing the faulty position is an essential element of any interconnect test. Generally, the interconnect test algorithms that need a short test time cannot perform the complete diagnosis and the algorithms that perform the complete diagnosis need a lengthy test time. To overcome this problem, a new interconnect test algorithm is developed. The new algorithm can provide the complete diagnosis of all faults with a shorter test time compared to the previous algorithms.     

Structural design optimization for board-level drop reliability of wafer-level chip-scale packages

In this paper, the Taguchi optimization method is applied to obtain the optimal design in enhancing board-level drop reliability of a wafer-level chip-scale package (WLCSP) under JEDEC drop test condition B, which features a half-sine impact acceleration pulse with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. An L₉ (3⁴) orthogonal array is arranged for the optimization of four control factors that involve compositions of solder alloys and thickness of die and polyimide passivation layers. The submodeling technique capable of dealing with path-dependent features, including elastoplastic responses of solder joints and structural nonlinearity under drop impacts, is applied so that delicate structures of passivation, under bump metallurgy (UBM), and redistribution line (RDL) in a WLCSP package can be taken into account. Effects of these control factors on the drop reliability of WLCSP are compared and ranked.     

Electrical test strategies for a wafer-level packaging technology

A wafer-level packaging (WLP) technology is under development that provides compliant electrical leads with a density as high as 12,000 per cm/sup 2/. The leads are batch processed while the integrated circuits are still in wafer form through a series of relatively simple photolithographic steps. After electrical testing, the wafers are diced and the integrated circuits (ICs) are ready for direct assembly to an interconnect substrate. Sufficient lateral and vertical compliance is provided by the leads to accommodate the nonplanarity encountered during assembly and the thermal mismatch between the IC and substrate during normal operation. The high density of compliant leads presents both challenges and opportunities for electrical testing. This paper first summarizes the process technology used to fabricate these high-density electrical contacts. Several potential test strategies are then introduced that may take advantage of these contacts.     

A software tool to support the reliability design and evaluation oftelecommunication networks

Highly reliable telecommunication networks require new technologies, such as the reliability specification, design, and evaluation method used at NTT. This paper describes the basic concepts of this method, and the ARDES-NET (Availability Reliability Design and Evaluation System for NETworks) software tool is used to support the reliability design and evaluation. ARDESNET has a user-friendly interface and can be easily put into practice     

Sequence test method for reliability evaluation of semiconductor devices

The failure-rate λ, of a device can be determined using Arrhenius model $\text{λ = A}\text{e}{}^{\mathrm{<mtext>?E</mtext><mtext>KT</mtext>}}$. The number of thermal cycles a device can withstand can be postulated using an exponential model, N = g e^?aT. Based on these models, a “sequence” process of thermal-fatigue and life tests is arrived at, which makes use of a mathematical equation giving the rate of decay of MTBF relative to the number of thermal-cycles, $\text{δ = P}\text{exp}\text{[p · ΔT + (}\text{q}\text{T}\text{)]}$. In other words, MTBF of the devices can be reduced by pre thermal cycling.     

Nanomechanical analyses of porous SiO2 low-dielectric-constant films for evaluation of interconnect structure reliability

Porous SiO₂ low-dielectric-constant films containing different porosities and sizes of uniformly distributed pores were prepared in this study. Their nanomechanical properties including true flow stress and fracture toughness were analyzed by a nanoindentation test. The hardness and elastic modulus of the films prepared with an ethanol molar ratio of 3 and an aging time of 16 h reached maximum values of 2.4 and 40 GPa, respectively. With increasing ethanol molar ratio, the porosity increased, and the mechanical properties consequently decreased. With increasing aging time, the mechanical properties increased and then dropped due to enlarged pore sizes. From converted true flow stress, the porous SiO₂ films were found to yield at an ultimate stress of 3.1 GPa, and the maximum fracture energy release rate was calculated as 3.4 J/m². The plastic deformation and fracture behavior of the porous films was observed through crack initiation and propagation along the large amount of pores.     

An evaluation of test methods for the detection and control ofinterconnect reliability

A number of fast, wafer-level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of the interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated, and the results are compared with package-level median time to failure (MTF) results. The isothermal test method combined with standard wafer-level electromigration accelerated test (SWEAT)-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over short test times     

Investigation of electromigration reliability of redistribution lines in wafer-level chip-scale packages

Wafer-level chip-scale packages (WLCSPs) have become subject to the same drive for miniaturization as all electronic packages. The I/O count is increasing and ball pitch is shrinking at the expense of trace pitch and in turn, current densities are increasing. This leads to current crowding and Joule heating in the vicinity of solder joints and under bump metallurgy (UBM) structures where resistance values change significantly. These phenomena are responsible for structural damage of redistribution line (RDL)/UBM and UBM/solder interconnects due to ionic diffusion or electromigration. In this work, sputtered Al and electroplated Cu RDLs were examined and quantified by three-dimensional electrothermal coupling analysis. Results provide a guideline for estimating maximum allowable currents and electromigration lifetime.     

NTP-SIOT: A test tool for advanced mobile services

This article describes system design for an Open Mobile Alliance Service Interoperability Test Platform called NTP-SIOT. Based on the TTCN-3 specifications, we show how 4G mobile applications such as OMA multimedia messaging service can be tested in this platform     

IC test structures for multilayer interconnect stress determination

A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results     

Study of complete interconnect reliability for a GaAs MMIC power amplifier

By combining the finite element analysis (FEA) and artificial neural network (ANN) technique, the complete prediction of interconnect reliability for a monolithic microwave integrated circuit (MMIC) power amplifier (PA) at the both of direct current (DC) and alternating current (AC) operation conditions is achieved effectively in this article. As a example, a MMIC PA is modelled to study the electromigration failure of interconnect. This is the first time to study the interconnect reliability for an MMIC PA at the conditions of DC and AC operation simultaneously. By training the data from FEA, a high accuracy ANN model for PA reliability is constructed. Then, basing on the reliability database which is obtained from the ANN model, it can give important guidance for improving the reliability design for IC.     

Copper wire interconnect reliability evaluation using in-situ High Temperature Storage Life (HTSL) tests

This paper describes the use of in-situ High Temperature Storage Life (HTSL) tests based on a four point resistance method to evaluate Cu wire interconnect reliability. Although the same set up was used in the past to monitor Au–Al ball bond degradation, a different approach was needed for this system. Using conventional statistical methods of failure probability distributions and a fixed failure criterion were found to be unsuitable in this case. Besides this, tests usually take very long until a sufficient percentage of the population have failed according to that criterion. A simple physical model was used to electrically quantify ball bond degradation due to the prevailing failure mechanism in a substantially smaller amount of test time. The method enabled the determination of activation energies for a number of moulding compounds and is extremely useful for a fast screening of such materials regarding their suitability for Cu wire.     

A new electromigration testing technique for rapid statistical evaluation of interconnect technology

We describe a test structure and a testing technique that allows simultaneous stressing of 50 or more parallel thin film lines of the same width. This technique allows determination of the mean time to electromigration-induced failure and the deviation in the time to failure in a single test. This technique allows more rapid statistical evaluation of new or modified interconnect technologies.     

A wafer-level hermetic encapsulation for MEMS manufacture application

In order to simplify the processing complexity and cut down the manufacturing cost, a new wafer bonding technique using ultraviolet (UV) curable adhesive is introduced here for microelectromechanical systems (MEMS) device packaging and manufacturing applications. UV curable adhesive is cured through UV light exposure without any heating process that is suitable for the packaging of temperature-sensitive materials or devices. A Pyrex 7740 glass is chemically wet etched to form microcavities and utilized as the protection cap substrate. After a UV-curable adhesive is spin-coated onto the glass substrate, the substrate is then aligned and bonded through UV light exposure with a device substrate below. Electrical contact pad opening and die separation are done simultaneously by dicing. Two different testing devices, a dew point sensor and capacitive accelerometer, are built to evaluate the package strength and hermeticity. After the dicing process, no structural damage or stiction phenomenon is found in the packaged parallel capacitor. The acceleration test results also indicate that the package using the Loctite 3491 UV adhesive with 150 /spl mu/m bond width can survive more than 300 days at a 25/spl deg/C and 100% relative humidity working environment.     

Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages

In this paper we study board-level thermomechanical reliability of a wafer-level chip-scale package subjected to an accelerated thermal cycling test condition. Different control factors are considered for a robust design towards enhancement of the thermal fatigue resistance of solder joints. These factors include diameter, pitch, and standoff of the solder joints, size of the solder connection opening on the die side, thickness of the pad on the test board, thickness of the test board, and dimension of the die. The Taguchi method along with the technique of analysis of variance are applied in the robust design process. Importance of these factors on the thermomechanical reliability of the package is ranked and the resulting robust design is further verified.     

Permanent and single event transient faults reliability evaluation EDA tool

In nanotechnology domain, reliability is a fundamental concern in the design and manufacturing process of VLSI circuits. Thus, this paper presents a tool developed to evaluate the reliability of logic cells in order to provide a set of information to improve design robustness. The tool is able to evaluate logic cells under Single Event Transient (SET) faults and, also, permanent faults such as Stuck-On (SOnF) and Stuck-Open (SOF). The information produced by this tool help designers to choose the most reliable cells to be adopted in their designs.