A 16 bit/spl times/16 bit pipelined multiplier macrocell

A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfiguration of the basic array can be performed. The multiplier macrocell measures 1.7 mm/spl times/1.7 mm.     

A high-speed high-density silicon 8/spl times/8-bit parallel multiplier

An 8/spl times/8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61/spl times/0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.     

A 230-MHz half-bit level pipelined multiplier using truesingle-phase clocking

An 8-bit×8-bit signed two's complement pipelined multiplier megacell implemented in 1.6-μm single-poly, double-metal N-well CMOS is described. It is capable of throughputs of 230,000,000 multiplications/s at a clock frequency of 230 MHz, with a latency of 12 clock cycles. A half-bit level pipelined architecture, and the use of true single-phase clocked circuitry are the key features of this design. Simulation studies indicate that the multiplier dissipates 540 mW at 230 MHz. The multiplier cell has 5176 transistors, with dimensions of 1.5 mm×1.4 mm. This multiplier satisfies the need for very high-throughput multiplier cores required in DSP architectures     

Micro/370: a 32-bit single-chip microprocessor

A 32-bit single-chip microprocessor is described that directly implements 102 System/370 instructions and supports the emulation of the rest of the instructions. It is fabricated using a 2-/spl mu/m polysilicon-gate NMOS technology with two levels of aluminium. The chip is 10/spl times/10 mm/SUP 2/ with 200000 transistor sites. It is designed for a 10-MHz clock at worst case and has been operated at 18 MHz with a 3-W power dissipation. The design and verification methodologies and the testing consideration are also described.     

A 14-bit, 10-Msamples/s D/A converter using multibit /spl Sigma//spl Delta/ modulation

A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-/spl mu/m CMOS technology and operates from a single 2.5-V supply.     

A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter

The analog-to-digital converter presented in this work demonstrates the efficiency of the straight 2.5 bit-per-stage approach for the implementation of pipelined switched-capacitor architectures targeting up to 16-bit resolution and 65-MS/s sampling rate. The test chip has been fabricated in a 45-GHz f/sub T/, 0.4-/spl mu/m 3.3-V SiGe BiCMOS process that makes it suitable for integration with an RF front-end toward an antenna-to-DSP communication processor. Performance of 78.3 dBFS SNR, 88dBc SFDR at 65 MS/s, 1 MHz input is obtained without trimming or calibration, dissipating 970 mW total with external references. Since the 4 V/sub p-p/ signal range chosen for high SNR could lead to distortion in the Sample/Hold and the pipelined quantizer with only 3.3-V supply, a fast and accurate SPICE simulation technique for INL investigation is described that enabled detailed diagnosis of potential nonlinearity sources. Theoretical analysis and practical implementation of the clock circuit are also discussed allowing the design of a CMOS-based clock featuring 180-fs jitter, which preserves high SNR against input frequency: state-of-the-art 73.5dBFS have been observed at 150 MHz input, popular intermediate frequency (IF) for single-heterodyne BTS receivers. Finally, the figures of merit encompassing power, effective resolution, and speed rank the dynamic performance of the ADC core among the best in its class.     

A 1.5 V CMOS 4-bit microcomputer needs only 100 /spl mu/W

Describes a new 4-bit microcomputer fabricated using a low-power silicon gate CMOS process and working from a supply voltage down to 1.2 V. The /spl mu/C can directly drive up to seven 3:1 multiplexed LCD digits, scan up 48 keys, and perform 4-bit handshaking data transfer with external devices. 16-bit, single-word instructions and eight stack levels permit efficient use of the 640-word ROM. Operating from a 4.19 MHz crystal, the device has an instruction cycle time of 15 /spl mu/s. An operating power of 100 /spl mu/W at 1.5 W makes the chip ideal for performing control and timing functions in battery operated applications.     

An 8-MHz CMOS subranging 8-bit A/D converter

A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.     

A 25 ns 8K /spl times/ 8 static MTL/I/SUP 2/L RAM

An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure.     

An 80-MHz 8-bit CMOS D/A converter

A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.     

A 500-MHz 8-bit D/A converter

An ultrafast monolithic 8-bit DAC is designed and fabricated. To realize this DAC, a new high-speed conversion technique, referred to as the data multiplexing method, and a variation of the segmented DAC (J.A. Shoeff, 1979) for low glitch are developed. The DAC is fabricated with shallow-groove-isolated 3-/spl mu/m VLSI technology with peak f/SUB T/'s of 4.5 GHz. An experimental 8-bit DAC features a conversion rate of over 500 MHz, a full-scale settling time to 1% of 2 ns, rise/fall times of 0.6 ns, and a glitch energy of 20 ps-V without input latches or a deglitcher.     

A 2K/spl times/8-bit static MOS RAM with a new memory cell structure

A 2K/spl times/8-bit static MOS RAM with a new memory cell structure has been developed. The memory cell consists of six devices including four MOSFETs and two memory load resistors. Two load resistors are fabricated in the second-level polysilicon films over the polysilicon gate MOSFET used as the driver. Thus the memory cell area is determined only by the area of four MOSFETs. By applying the new cell structure and photolithography technology of 3 /spl mu/m dimensions, the cell area of 23/spl times/27 /spl mu/m and the chip area of 3.75/spl times/4.19 mm have been realized. The RAM is nonclocked and single 5 V operation. Access time of about 150 ns is obtained at a supply current of 120 mA.     

1.5 V 1 K-CMOS-RAM with only 8 pins

A 256-bit/spl times/4-bit static RAM working on a supply voltage down to 1.2 V is described. A serial interface for the address and the data with a 4-bit bus reduces the pincount of the RAM to only 8. Special design techniques to reach the design goal-very low power at a reasonable circuit speed-are discussed in detail. The device is fabricated in a low power silicon gate CMOS process. An operating power of 500 /spl mu/W/MHz and a standby power of less than 1 /spl mu/W at 1.5 V supply voltage was achieved. With this serial interface a cycle time of 1 /spl mu/s at 1.5 V was measured.     

A 32-bit VLSI CPU chip

A fully integrated 32-bit VLSI CPU chip utilizing 1 /spl mu/m features is described. It is fabricated in an n-channel silicon gate, self-aligned technology. The chip contains about 450000 transistors and executes microinstructions at approximately one per 55 ns clock cycle. It can execute a 32-bit binary integer add in 55 ns, a 32-bit binary integer multiply in 1.8 /spl mu/s, and a 64-bit floating point multiply in 10.4 /spl mu/s. The instruction set provides the functions of an advanced mainframe CPU. Because the implementation of such a complex device poses an organizational as well as a technical challenge, the design philosophy that was adopted is summarized briefly. Careful attention was paid to designer productivity, and design flexibility and testability.     

Design of a 3-V 300-MHz low-power 8-b×8-b pipelinedmultiplier using pulse-triggered TSPC flip-flops

This paper describes the design of a low-power pipelined multiplier. It is illustrated in this paper that the power consumption of the clocking system cannot be overlooked and the design of the storage element is the key to low power. A new pulse-triggered true single-phase clocking (TSPC) flip-flop (PTTFF) is proposed for this purpose in this design. The PTTFF features true single-phase clocking, simple structure, and high performance. One PTTFF comprises only five transistors with only one controlled by the clock. Using the PTTFF together with the 14-transistor pseudo-NMOS full adder, an 8-b×8-b pipelined multiplier has been designed and implemented, employing a 0.6-μm CMOS process. When the multiplier operates at the operating frequency of 300 MHz with VDD equal to 3.3 V, it dissipates only 53% of the power of the multiplier designed with nine-transistor TSPC flip-flops under the same operating conditions. When the supply voltage for the core array is reduced to 2.5 V, the multiplier can still work up to 300 MHz with only 47% of the power of the multiplier designed using the S and D full adders and C²MOS latches with VDD equal to 3.3 V. The chip has been fabricated, and the measured power is 52.4 mW when operated at 300 MHz and 3.3 V     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.     

A 14-bit delta-sigma ADC with 8/spl times/ OSR and 4-MHz conversion bandwidth in a 0.18-/spl mu/m CMOS process

A 14-bit 8/spl times/ oversampling delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter (ADC) for wide-band communication applications has been developed. By using a novel architecture, a high maximum out-of-band quantization noise gain (Q/sub max/) is realized, which greatly improves the SNR and tonal behavior. The ADC employs a fifth-order single-stage structure with a 4-bit quantizer. It achieves 82-dB SNDR and 103-dB SFDR at 4-MHz conversion bandwidth with a single 1.8-V power supply.     

A 4160-bit C4D serial memory

A 4160-bit serial memory chip has been designed, fabricated, and tested using as the basic memory cell the conductively connected charge-coupled device (CCD) or C4D. The chip includes an inverting regenerator every 65 bits and a reading tap every 130 bits. Also on-chip is a recirculating amplifier which senses the charge packet as it reaches the end of the register and feeds it back to the input. This means that once data has been written onto the chip, it will be retained as long as the regenerator supply and the two clocks are on. The chip has two multiplexed halves to obtain a data rate of twice the clock frequency. The active area of the chip is 12 mm/SUP 2/ or 2900 /spl mu/m/SUP 2/ per bit. Operation was obtained for arbitrary data streams at clock rates of 1 kHz to 1.6 MHz (3.2 MHz data rate). Power dissipation varies linearly with frequency and is 16 /spl mu/W per bit at the highest frequency. Maximum read latency is 80 /spl mu/s at this frequency. This performance demonstrates the feasibility of the C4D as a component for a medium speed large-scale memory.     

A self-testing 2-/spl mu/m CMOS chip set for FFT applications

A chip set for high-speed radix-2 fast Fourier transform (FFT) applications up to 512 points is described. The chip set comprises a (16+16)/spl times/(12+12)-bit complex number multiplier, and a 16-bit butterfly chip for data reordering, twiddle factor generation, and butterfly arithmetic. The chips have been implemented using a standard cell design methodology on a 2-/spl mu/m bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10 MHz, and are cascadable up to 512 points. The chips feature an offline self-testing capability.