薄膜双栅MOSFET体反型现象的研究

通过对QM模型的介绍，说明了薄膜双栅MOSFET体反型现象是量子效应的结果，并对QM模型中提出的反型层质心概念进行了剖析，阐述了其重要的物理意义和应用价值。利用反型层质心概念，提出了一组形式非常简单，且与体硅单沟道MOSFET表达式十分相似的薄膜双栅MOSFET亚阈值区反型层载流子浓度和亚阈值电流的表达式。与MEDICI模拟结果的比较证明了其精确性。应用反型层质心及所提出的亚阈值区模型，对薄膜双栅MOSFET体反型现象进行了深入的分析，提出了一个能够较好体现体反型作用的硅膜厚度范围。     

Effects of the inversion-layer centroid on the performance ofdouble-gate MOSFETs

The role of the inversion-layer centroid in a double-gate metal-oxide-semiconductor field-effect-transistor (DGMOSFET) has been investigated. The expression obtained for the inversion charge is similar to that found in conventional MOSFETs, with the inversion-charge centroid playing an identical role. The quantitative value of this magnitude has been analyzed in volume-inversion transistors and compared with the value obtained in conventional MOSFETs. The minority-carrier distribution has been found to be even closer to the interfaces in volume-inversion transistors with very thin films, and therefore, some of the advantages assumed for these devices are ungrounded. Finally, the overall advantages and disadvantages of double-gate MOSFET's over their conventional counterparts are discussed     

Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's

Inversion-layer capacitance has been experimentally characterized and identified to be the main cause of the second-order thickness-dependence of MOSFET characteristics. Field-dependent channel mobilities of both electrons and holes were independent of gate-oxide thicknesses from 50 to 450 Å, e.g., there is no evidence of the alleged mobility degradation in very thin gate-oxide MOSFET's. Subthreshold slope, insignificantly affected by the inversion-layer capacitance, follows the simple theory down to ∼ 35 Å of oxide thickness. The empirical equations for inversion-layer Capacitance and mobilities versus electric field are proposed.     

A note on the equality of bulk and inversion-layer capacitance at threshold

Analyses of the MOSFET have shown that there exists at least an approximate equality between bulk capacitance and inversion-layer capacitance at the threshold of strong inversion, but no physical explanation for this relationship has been put forward. The physical picture offered below shows that within the limits of the customary approximations and assumptions, these two capacitances are precisely equal at threshold.     

施主能级分裂对SiC基p-MOSFET反型层电荷的影响

通过引进基态施主能级分裂因素,对SiC基p-MOSFET的反型层电荷模型进行了改进。经计算发现,在考虑到能级分裂后反型层电荷面密度降低,并且能级分裂的影响随栅电压绝对值的增加而减弱。在阈值电压处,能级分裂对反型层电荷的影响随掺杂浓度的增加而增强,随温度的提高而减弱,同时也与杂质能级深度相关。在能级分裂影响下阈值电压的绝对值增加,不过增量较小。     

On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs

An analytical total gate capacitance C/sub G/ model for symmetric double-gate (DG) and fully depleted silicon-on-insulator (FD/SOI) MOSFETs of arbitrary Si film is developed and demonstrated. The model accounts for the effects of carrier-energy quantization and inversion-layer screening and is verified via self-consistent numerical solutions of the Poisson and Schro/spl uml/dinger equations. Results provide good physical insight regarding C/sub G/ degradation due to quantization and screening governed by device structure and/or transverse electric field for nanoscale DG and FD/SOI MOSFETs. Two limits of C/sub G/ at ON-state are then derived when the silicon film t/sub Si/ approaches zero and infinity. The effect of inversion-layer screening on C/sub G/, which is significant for ultrathin Si-film DG MOSFETs, is quantitatively defined for the first time. The insightful results show that the two-dimensional screening length for DG MOSFETs is independent of the doping density and much shorter than the bulk Debye length as a result of strong structural confinement.     

Influence of the interface-state density on the electron mobility in silicon inversion layers

The electron inversion-layer mobility in a metal oxide semiconductor field effect transistor, as a function of the transverse electric field, has been studied in the temperature range 13–300K for different interface-state densities. Experimental data are in excellent agreement with a simple semi-empirical model. However, the term attributed by other authors to phonon scattering depends on the interface-state density, even at high temperatures, and becomes negative at low temperatures. These facts are shown to be a consequence of the dependence of coulomb scattering on the transverse electric field.     

Transconductance degradation in thin-Oxide MOSFET's

In this work we investigate the transconductance degradation effect which occurs in thin-oxide FET's due to the finite inversion-layer capacitance and to the decrease of the electron mobility as the electric field increases. Experimental capacitance and charge measurements are performed at room and at liquid-nitrogen temperature on 10-nm oxide FET's, and the data are compared with a classical and a quantum-mechanical model extended to take into account the non-uniform doping profile in the silicon substrate. Accurate mobility determinations are performed accounting for the nonuniform distribution of the mobile charge along the channel, and a mobility expression against the average normal field is incorporated in a generalized Pao-Sah double-integral formula for the FET drain current. Design trade-offs for submicrometer FET's are finally discussed.     

Impact of electron and hole inversion-layer capacitance on lowvoltage operation of scaled n- and p-MOSFET's

The influence of inversion-layer capacitance (C_inv) on supply voltage (V_dd) of n- and p-MOSFET's is quantitatively examined. The physical origin of the effect of C_inv on V_dd consists in the band bending of a Si substrate in the inversion condition due to C_inv, which is not scaled with a reduction in gate oxide thickness. The amount and the impact of the band bending is accurately evaluated on a basis of one dimensional (1-D) self-consistent calculations including two-dimensional (2-D) subband structure of inversion-layer electrons and holes. It is demonstrated that additional band bending of a Si substrate due to C_inv becomes a dominant factor to limit the lowering of V_dd for CMOS with ultrathin gate oxides. The operation at V_dd lower than 0.6 V is quite difficult even with effective T_ox less than 1 nm     

Trapped charge distributions in thin (10 nm) SiO2 filmssubjected to static and dynamic stresses

Thin (10 nm) gate oxide MOS capacitors have been subjected to static and dynamic stress conditions. The evolution of the trapped charge distributions (characterized by average density and centroid) has been measured as a function of the stress time. The evolution of the average charge density for DC stresses shows that both polarities have identical trap generation rates and a constant average density of traps at breakdown. However, the final density of traps is much smaller for injection from the gate, so that the time-to-breakdown is also much shorter for this stress polarity. The evolution of the centroid shows that traps are always mainly generated near the cathodic interface. Unipolar dynamic stresses give results which are qualitatively very similar to those obtained under DC conditions and without a relevant frequency dependence. In contrast, bipolar stress experiments show significant qualitative differences, the frequency dependence being very important. In general, the trap generation and trapping rates are reduced in comparison to the DC and unipolar cases, this reduction being more important at high frequencies. In addition, the average density of trapped electrons at the breakdown is larger than that obtained in DC experiments. Both observations explain the tremendous increase in the mean-time-to-breakdown obtained under high-frequency stress conditions. The presented results are qualitatively explained in terms of microscopic degradation models     

Subthreshold transconductance in the long-channel MOSFET

The transconductance-current ratio of the long-channel MOSFET approaches the ideal value of q/kT under subthreshold conditions. This behavior has previously been explained using a BJT-like model. It is shown that such a model is inappropriate, and that this phenomenon can be explained by the diffusive nature of the subthreshold current, the law governing the density gradient, and the existence of a quasi high-low junction between the source region and channel. A general expression for subthreshold transconductance is developed. It is also demonstrated analytically that the bulk and inversion-layer capacitances that enter into this expression are equal at the threshold of strong inversion, a demonstration that avoids approximations employed in a previous treatment of the matter.     

Electron trapping in SiO2 formed by oxygen implantation

Electron trapping in implanted oxides has been investigated using avalanche electron injection on a silicon/oxide/silicon capacitor structure. Analysis of the capacitance/voltage curves, yields capture cross sections of 8×10^-15 and 1×10^-16 cm². Moreover, the authors show that as the structure is sensitive to surface potential changes at both oxide/silicon interfaces, the technique permits the density and the centroid of the trapped charge to be determined independently     

Influence of Si nanocrystal distributed in the gate oxide on the MOS capacitance

In this paper, the authors have studied the influence of silicon nanocrystal (nc-Si) distributed in the gate oxide on the capacitance for the circumstances that the nc-Si does not form conductive percolation tunneling paths connecting the gate to the substrate. The nc-Si is synthesized by Si-ion implantation. The effective dielectric constant of the gate oxide in the nc-Si distributed region is calculated based on a sublayer model of the nc-Si distribution and the Maxwell-Garnett effective medium approximation. After the depth distribution of the effective dielectric constant is obtained, the MOS capacitance is determined. Two different nc-Si distributions, i.e., partial and full nc-Si distributions in the gate oxide, have been considered. The MOS capacitance obtained from the modeling has been compared to the capacitance measurement for a number of samples with various gate-oxide thicknesses, implantation energies and dosages, and an excellent agreement has been achieved for all the samples. A detailed picture of the influence of implantation energy and implantation dosage on the MOS capacitance has been obtained.     

An analytical model for discretized doped InAlAs/InGaAs heterojunction HEMT for higher cut-off frequency and reliability

In the proposed work the model has been formulated for discretized doped HEMT, where the conventional uniformly doped, pulsed doped and delta doped structure are the special cases. An expression for sheet carrier density has been formulated considering the effect of doping-thickness product and has been extended to calculate drain current, transconductance, capacitance and cut-off frequency of the device. The model also takes into account the non-linear relationship between sheet carrier density and quasi Fermi energy level to validate it from subthreshold region to high conduction region. The results so obtained have been compared with pulsed doped structure to validate the model. The analysis concentrates on the distance of doping from the heterojunction and gate electrode. Different design criteria have been given to dope the carriers (amount and distance) in different regions to optimize the performance for higher sheet carrier density/parallel conduction voltage/effective parallel conduction voltage (V_c−V_off) to increase the transconductance, cut-off frequency and reliability of the device.     

Study of the effects of a stepped doping profile in short-channelMOSFETs

The performance of a stepped doping profile for improving the short-channel behavior of a submicrometer MOSFET has been analyzed in detail by using a quasi-two-dimensional (quasi-2-D) MOSFET simulator including inversion-layer quantization coupled with a one-electron Monte Carlo simulation. Several second-order effects, such as mobility degradation both by bulk-impurity and interface traps, carrier-velocity saturation, and channel-length modulation, have been included in the simulator. Very good agreement between experimental and simulated results is obtained for short-channel transistors. It has been shown that including a low-doped zone of convenient thickness next to the interface over a high doping substrate improves both the electron mobility and the threshold voltage of the device, while avoiding short-channel effects. The use of simulation has allowed us to study certain kinds of devices without needing to make them     

An analytical a-Si:H TFT DC/capacitance model using an effectivetemperature approach for deriving a switching time model for an invertercircuit considering deep and tail states

This paper presents an analytical a-Si:H DC/capacitance model using an effective temperature approach for deriving a switching time model for an inverter circuit considering deep and tail states. Using an effective temperature approach, the localized deep and tail states have been considered in the DC/capacitance model and the switching time model. As verified by the published data, the analytical DC/capacitance model provides an accurate prediction. Based on the analytical model, the threshold voltage of an a-Si:H TFT is proportional to the deep state density and the switching time of the TFT-inverter is dependent on the tail state density     

Charge-sheet model for silicon carbide inversion layers

The charge-sheet model for metal-oxide-semiconductor (MOS) inversion layers is extended to silicon carbide. The generalized model is based on an analytical solution of the Poisson equation for the case of incomplete ionization of dopant impurities and incorporating Fermi-Dirac statistics. The results are compared with the conventional charge-sheet model which assumes complete impurity ionization and nondegenerate statistics. It is found that, at room temperature and for gate voltages in weak and moderate inversion, the present model predicts higher inversion-layer charge density at a given gate voltage. However, the relationship between the inversion charge and the surface Fermi potential is essentially independent of the degree of impurity ionization. In strong inversion or at temperatures above ~600 K, the differences between the two models are small. A formula is given for the threshold voltage as a function of the impurity ionization energy. The effects of several different interface state energy distributions on inversion charge are investigated. It is found that a slowly-varying interface-state density has an effect on threshold voltage of a MOSFET similar to that of a fixed oxide charge, while an interface-state density that increases at least exponentially with energy has the effect of lowering the field-effect mobility and transconductance     

Investigation and modeling of stressed thermal oxides

A comprehensive picture of SiO₂ degradation after electrical stress is proposed, starting from a kinetics model of defect creation. Two different techniques have been used to monitor changes in oxides: (1) a current–voltage technique (I–V) focused on the investigation of the stress induced leakage current in MOS capacitors, and (2) a frequency-resolved capacitance technique. The value of defect density (N) yielded by the kinetics model has been used as the input of a trap assisted tunnel (TAT) model and gave low-field current curves which fit experiments remarkably good. The same value of N has been also used in a model of differential capacitance and gave excellent fits of low-frequency capacitance data, involving tunnel in slow traps located at the silicon interface. Dependence of the low-field current and low-frequency capacitance on the stress conditions were also modeled. Therefore, the kinetics model of defect creation used in conjunction with TAT model at low-fields and low-frequency capacitance gives an overall comprehension of stress induced changes in thermal oxides.