Thermal management of power electronics modules packaged by a stacked-plate technique

The research presented in this paper is part of a multidisciplinary research program of the Center for Power Electronics Systems at Virginia Tech. The program supported by the Office of Naval Research focuses on the development of innovative technologies for packaging power electronics building blocks. The primary objective of this research is to improve package performance and reliability through thermal management, i.e., reducing device temperatures for a given power level. The task of thermal management involves considering trade-offs in the electrical design, package layout and geometry, materials selection and processing, manufacturing feasibility, and production cost. Based on the electrical design of a simple building block, samples of packaged modules, rated at 600 V and 3.3 kW, were fabricated using a stacked-plate technique, termed metal posts interconnected parallel plate structure (MPIPPS). The MPIPPS technique allows the power devices to be interconnected between two direct-bond copper substrates via the use of metal posts. Thermal modeling results on the MPIPPS packaged modules indicate that the new packaging technique offers a superior thermal management means for packaging power electronics modules.     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

Three-Dimensional Packaging for Power Semiconductor Devices and Modules

Demands for increasing power density and levels of functional integration in switch-mode power converters require power electronics manufacturers to develop innovative packaging solutions for power semiconductor devices and modules. Three-dimensional (3-D) packaging techniques offer the potential of lower resistance, higher current handling capability, smaller volume, better thermal management capability, and high reliability. In this paper, we present the constructions and some electrical and thermomechanical analyses of four 3-D packaging approaches that have been developed within the Center for Power Electronics Systems—an NSF Engineering Research Center.     

Flip-chip on flex integrated power electronics modules for high-density power integration

Three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications. In this FCOF-IPEM structure, solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides. One side of the flex provides interconnection to power devices while the other is used to construct a simple gate-drive circuit; via holes through the flex integrate the power stage and gate-drive together. Solder-bumped MOSFET devices were obtained by a metallization processing and were used in the FCOF power module construction to improve thermal performance, power density, and integration. With this packaging approach, the multiple solder bumps, instead of the thin, long bonding wires were utilized to connect the power devices to the flex substrate and to improve heat dissipation, lower parasitic oscillations, and reduce package size. Reliability of solder joints has been dealt with through selection of materials, such as use of flexible substrates and underfill encapsulation, and design of joint shape for lower thermomechanical stresses. A comparative study of continuous switching test results have shown that the FCOF-IPEMs have better electrical performance than commercial wire bonded power modules.     

Design for reliability of power electronics modules

Power electronics uses semiconductor technology to convert and control electrical power. Demands for efficient energy management, conversion and conservation, and the increasing take-up of electronics in transport systems has resulted in tremendous growth in the use of power electronics devices such as Insulated Gate Bipolar Transistors (IGBT’s). The packaging of power electronics devices involves a number of challenges for the design engineer in terms of reliability. For example, IGBT modules will contain a number of semiconductor dies within a small footprint bonded to substrates with aluminum wires and wide area solder joints. To a great extent, the reliability of the package will depend on the thermo-mechanical behavior of these materials. This paper details a physics of failure approach to reliability predictions of IGBT modules. It also illustrates the need for a probabilistic approach to reliability predictions that include the effects of design variations. Also discussed are technologies for predicting the remaining life of the package when subjected to qualification stresses or in service stresses using prognostics methods.     

用于雷达发射机的140kW高压开关电源

现代电力电子学技术的迅速发展和大功率开关器件的出现使开关稳压电源在中功率雷达发射机中得到了广泛应用。目前,由于ＩＧＢＴ模块的推广应用和新的拓看望 技术的不断涌现,高压大功率开关稳压电源已开妈在现代雷达发射机中使用。本文简单介绍了１４０ＫＷ大在电源在某空间目标测量雷达发射机中的应用和其工程设计考虑。     

功率模块封装结构及其技术

本文从封装角度评估功率电子系统集成的重要性。文中概述了多种功率模块的封装结构形式及其主要研发內容。另外还讨论了模块封装技术的一些新进展以及在功率电子电路系统集成中的地位和作用。     

A NOVEL OVER—VOLTAGE PROTECTION METHOD FOR 600V SPIC

A novel over-voltage protection method for 600V BPIC(Smart Power IC) is proposed in this paper.The combining FFLRs(Floating Field Limiting Rings) system is designed to be a voltage detector.The detector‘s voltage can turn off the switch of the APFC(Active Power Factor Correction )Circuit and the bus voltage would fall from 600VDC to 300VDC,so the SPIC and power devices can be protected.The advantages of this design are that the total protection circuits are integrated in SPIC and technologically compatible with CMOS or BCD(Bipolar CMOS-DMOS) technology.     

Tiny-scale “stealth” current sensor to probe power semiconductor device failure

“Stealth” electric current probing technique for power electronics circuits, power device modules and chips makes it possible to measure electric current without any change or disassembling the circuit and the chip connection for the measurement. The technique consists of a tiny-scale magnetic-field coil, a high speed analog amplifier and a digitizer with numerical data processing. This technique can be applied to a single bonding wire current measurement inside IGBT modules, chip scale current redistribution measurement and current measurement for surface mount devices. The “stealth” current measurement can be utilized in the failure mechanism understanding of power devices including IGBT short circuit destruction.     

Recyclable,Flexible, Low‐Power Oxide Electronics

The ability to process and dimensionally scale field‐effect transistors with and on paper and to integrate them as a core component for low‐power‐consumption analog and digital circuits is demonstrated. Low‐temperature‐processed p‐ and n‐channel integrated oxide thin‐film transistors in the complementary metal oxide semiconductor (CMOS) inverter architecture are seamlessly layered on mechanically flexible, low‐cost, recyclable paper substrates. The possibility of building these circuits using low‐temperature processes opens the door to new applications ranging from smart labels and sensors on clothing and packaging to electronic displays printed on paper pages for use in newspapers, magazines, books, signs, and advertising billboards. Because the CMOS circuits reported constitute fundamental building blocks for analog and digital electronics, this development creates the potential to have flexible form factor computers seamlessly layered onto paper. The holistic approach of merging low‐power circuitry with a recyclable substrate is an important step towards greener electronics.     

Analysis,design and implementation of an interleaved three-level PWM DC/DC ZVS converter

This paper presents a new parallel three-level soft switching pulse-width modulation (PWM) converter. The proposed converter has two circuit cells operated by the interleaved PWM modulation. Thus, the ripple currents at input and output sides are reduced. Each circuit cell has two three-level zero voltage switching circuits sharing the same power switches. Therefore, the current and power rating of the secondary side components are reduced. Current double rectifier topology is selected on the secondary side to decrease output ripple current. The main advantages of the proposed converter are soft switching of power switches, low ripple current on the output side and low-voltage rating of power switches for medium-power applications. Finally, the performance of the proposed converter is verified by experiments with 1 kW prototype circuit.     

Modeling and design of a monolithically integrated power converter on SiC

To fully explore the high temperature and high power density potential of the 4H-SiC material, not only power devices need to be fabricated on SiC, but also the circuitries for signal generation/processing, gate driver and control. In this paper, static and dynamic characteristics of SiC lateral JFET (LJFET) devices are numerically simulated and compact circuit models developed. Based on these models, analog and digital integrated circuits functional blocks such as OPAMP, gate driver and logic gates are then designed and simulated. Finally, a fully integrated power converter including pulse-width-modulation circuit, over-temperature protection circuit and a power boost converter is designed and simulated. The converter has an input of 200 V and an output voltage of 400 V, 2.5 A, operating at 1 kW and 5 MHz.     

一种基于GaN器件大功率双向DC/DC变换器

本文介绍了一种新的高功率双向隔离式DC/DC变换器。DC/DC转换器使用基于氮化镓(GaN)的功率开关器件。本文对10 kW GaN大功率DC/DC变换器的拓扑结构进行了优化,参数化和分析,并通过仿真和验证了其有效性。它由两个单相全桥电路、两个输入输出电感和一个高频变压器组成。高频变压器在实现两个全桥变换器之间的电流隔离方面起着至关重要的作用。使用MATLAB仿真软件对10 kW的变换器进行了建模。MATLAB仿真结果验证了变换器的性能适合于高功率应用并能实现轻负载条件下的零电压开通(ZVS)和零电流关断(ZCS)。然后,设计了一个7 kW的实验原型,以验证所设计拓扑的有效性。     

Modern Laboratory-Based Education for Power Electronics and Electric Machines

Power electronics and motor drives are appropriate subjects for an advanced undergraduate or beginning graduate course. The subject is largely application-driven but draws from a broad knowledge base including basic circuits and electronics, control systems, power systems, and semiconductor devices. For many students, a power electronics laboratory can provide an early experience in synthesis, requiring them to use knowledge across their full curriculum with close attention to detail.     

Integrating active, passive and EMI-filter functions in power electronics systems:a case study of some technologies

Assemblies of power semiconductor switches and their associated drive circuits are at present available in modules. Upward into the multi-kilowatt range, mixed mode module construction is used. This incorporates monolithic, hybrid, surface mount, and wirebond technology. However, a close examination of the applications in motor drives and power supplies indicates that there has been no dramatic volume reduction of the subsystem. The power semiconductor modules have shrunk the power switching part of the converter, but the bulk of the subsystem volume still comprises the associated control, sensing, electromagnetic power passives (inductors, transformers, capacitors) and interconnects. This paper addresses the improvement of power processing technology through advanced integration of power electronics. The goal of a subsystem in a module necessitates this advanced integration, incorporating active switching stages, electromagnetic interference (EMI) filters, and electromagnetic power passives into modules by integration technology. The central philosophy of the technology development research in the National Science Foundation Engineering Research Center for Power Electronic Systems is to advance the state of the art by providing the concept of integrated power electronics modules (IPEMs) for all these functions. The technology underpinning such an IPEM approach is discussed.     

倒装芯片集成电力电子模块的热设计

将倒装芯片(Flip Chip, FC)技术引入三维集成电力电子模块(Integrated Power Electronic Module,IPEM)的封装,可构建FC-IPEM.在实验室完成了由两只球栅阵列芯片尺寸封装MOSFET和驱动、保护等电路构成的半桥FC-IPEM.针对半桥FC-IPEM,建立半桥FC-IPEM的一维热阻模型,分析模块主要的热阻来源.运用FLOTHERM软件进行三维仿真,得到模块温度分布结果,给出优化模块热性能的依据.     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

Thermal-aware design and fault analysis of a DC/DC parallel resonant converter

In this paper a 3-D electrothermal (ET) analysis of a DC–DC parallel resonant converter (PRC) for constant current (CC) application is presented. A full 3-D ET simulation approach is proposed at application level to provide a support for the design stage and to analyse possible fault conditions inside the active devices. Simulations and measurements have been performed on a 100 W–2 A prototype of a PRC-CC circuit with 80 kHz nominal switching frequency.In particular, in the reported case study, the analysis has been focused on the full-bridge section of the circuit in order to prove the effect of the soft switching operation, introduced by the resonant technique, and consider the effect of possible fault conditions. To this purpose an unexpected short-circuit condition on a power MOSFET composing the H-bridge is considered, to evaluate the ET circuit behaviour and the time-to-failure of the power section. Considerations are carried out in terms of minimum requirements of protection circuits which must be fulfilled in order to avoid catastrophic system failure.A second power converter, rated for 1.5 kW, has been then designed, based on the same circuital topology, and an ET simulation has been performed in order to carry out considerations on the effect of mismatches among the input bridge devices.     

Power electronics cooling effectiveness versus thermal inertia

Today, the popularity of power electronics integration is increasing. Despite the prospect of fully integrated module, including features like driving and control electronics, protection, power integration has not taken-off for medium to high power electronics applications. Manufacturing issues such as yield, reliability and return-on-investment for a new fabrication line are the major blocking points. As a first step toward integrated modules, integration of the cooling system appears realistic and cost effective. Increasing the cooling effectiveness could double the output current of an inverter while using the same amount of silicon. On the other hand, integrated cooling leads to small thermal inertia, which can generate high temperature variation under load cycling condition. This paper highlights the relationship between cooling effectiveness and thermal inertia. Typical performances of several cooling systems are compared under load cycling condition to explain how to take into account the variation of the losses in the choice of a cooling technique at the design stage. As an example, a standard liquid cooled plate performed similar to an integrated microchannel network for specific load variation frequencies.