High Performance CMOS Transconductor for Mixed-Signal Analog-Digital Applications

This paper describes a CMOS building block dedicated to high performance mixed analog-digital circuits and systems. The circuit consists of six MOS transistors realizing a new wideband and tunable transconductance. The theory of operation of this device is presented and the effects of transistor nonidealities on the global performances are investigated. Use of the proposed circuit to realize tunable functions (Gm-C filter and current opamp) is illustrated. HSPICE simulations show a wide tuning range of the transconductance value from 40 S to 950 S (500 S) for ±2.5 V (±1.5 V) supply voltages. The transconductance value remains constant up to frequencies beyond 500 MHz. The bandpass filter built with few transconductance blocks and capacitances was simulated with ±2.5 V supply voltage, the center frequency is tunable in the range of 30 MHz to 110 MHz. However, the opamp, which is designed with a transresistance-transconductance architecture, was simulated with ±1.5 V supply voltage. The gain of the opamp can be tuned between 70 dB and 96 dB and high gain-bandwidth product of 145 MHz has been achieved at power consumption of less than 0.5 mW. Experimental results on a fabricated transconductor chip are provided.     

Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |V _t |+2 V _ds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 m N-well process with a 3 V supply are given.     

IC Voltage to Current Transducers with Very Small Transconductance

This paper deals with the design of very small ac transconductance voltage to current transducers intended for the design of low frequency continuous-time filters, very large resistors and other applications. The first type of Operational Transconductance Amplifiers (OTA) is based on a triode biased transistor and a current division technique. The second one uses partial positive feedback which allows to reduce transistor dimensions but the sensitivity to transistor mismatches increases. The proposed techniques can be used for the design of high-order low frequency IC filters, ladder or based on biquads, with moderated transistor dimensions while the dynamic range-cutoff frequency performance is comparable to previously reported structures. A 10 Hz third order lowpass ladder filter has been designed with these techniques, and it shows a dynamic range of 62 dB. Besides, a novel biasing technique for capacitive sources coupled preamplifiers is proposed. Experimental results for a prototype, fabricated in a 1.2 m 1 level below 15 _RMS and dynamic range of 63 dB. The power consumption is only 10 watts and the supply voltages are ± 1.5 volts.     

Novel Voltage-Tunable, Low-Voltage Linear CMOS Transconductor

A novel voltage-tunable, low-voltage linear CMOS transconductor design is described. The design is based on the improvement of the cross-coupled pairs. SPICE simulation results show that using BSIM models, MOSIS 2-m n-well process parameters and a power supply of ±2.5 V, the linearity error is less than 0.4% over a differential input voltage range of ±1.2 V. The THD for a differential input voltage of 1V _pp at 1 kHz is 1.3%.     

A high-linear wide-tunable CMOS transconductor for video frequency applications

In this paper a new CMOS transconductor structure based on a g_m-boosted degenerated differential pair is presented for applications in the video frequency range. The proposed circuit combines two techniques, a switchable array of source degenerating MOS resistors and a programmable output current mirror, in order to widen the G_m tuning range while maintaining linearity. Degeneration MOS resistors are made common-mode voltage independent thanks to a simple control circuit. Post-layout simulation results from a 0.35 μm design supplied at 3.3 V show a wide tuning range (10–100 MHz), good linearity (−58.4 dB for an output signal voltage of 1.1 V_p–p) and low excess phase (<0.5° over the whole tuning range).     

High Performance CMOS Analog Arithmetic Circuits

Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V₁ + V₂), subtraction (V₂ – V₁), add/invert –(V₁ + V₂), and multiply (V₁ × V₂). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 m CMOS technology.     

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large- and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ _inv is controlled by the voltage differenceV _P – V_ch, whereV _ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV _P is defined as the particular value ofV _ch such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV _P – V_S andV _P – V_D. Using the charge sheet model with the assumption of constant doping in the channel, the drain currentI _D is derived and expressed as the difference between a forward componentI _F and a reverse componentI _R. Each of these is proportional to a function ofV _P – V_S, respectivelyV _P – V_D, through a specific currentI _S. This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.     

A CMOS transconductance element with improved DC gain and wide bandwidth for VHF applications

The design of a fully-differential, highly linear, voltage-tunable CMOS transconductance element with improved gain performance and wide bandwidth is described. A negative resistance technique for compensation of the parasitic output resistance of the transconductor circuit is employed without requiring extra internal nodes. As a result, dc-gain enhancement is obtained without any bandwidth penalty. SPICE simulations show that for a standard 3m CMOS technology with a power supply of ±5V, for most useful bias conditions THD is much lower than 1% for a 2V _RMS , 5MHz input sine wave; the tuning range of g _m is 36S to 265S. Finally the improved transconductance circuit is presented with an application to a transconductance-capacitor integrator with several tens of megahertz bandwidth.This work was supported in part by the State Scientific Research Committee, Poland, Grant No.8 S501 024 07, and by the National Science Foundation, USA, Grant No. MIP 91-21360.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

An Architectural Comparison and CMOS Implementation of Sixth-Order Cascaded ΣΔ Modulator

A sixth-order cascaded sigma-delta modulator isreported aiming low power data-converter architectures.Behavioral simulation shows that the cascaded (2-1-1-2)architecture is the most robust in terms of noiseperformance and accuracy. A prototype of this architecture was fabricated using a 2 m analogCMOS process. Measured results indicate that the modulator achieved 89 dB (14.8-b) peak in-bandsignal-to-noise ratio (SNR) and 92 dB (15.3-b) dynamicrange (DR) for a 32 kHz bandwidth, at a sampling rate ofonly 1 MHz. The modulator dissipated 79 mW from a±3.3 V supply voltage and only 45 mW from a±2.5 V supply voltage with negligible SNRdeterioration. Process scaling and supply-voltagescaling can thus drastically reduce power dissipationusing this architecture while maintaining high SNR andDR performance.     

Low-Voltage Differentiator for VHF Filtering

In this paper a G _m -C resonator circuit is proposed which is based on a new current-mode differentiating concept, compatible with low voltage and very high frequency operation.A prototype 4th-order 200 MHz band pass filter has been fabricated using a 0.8 m CMOS process and shows a side-band rejection lower than –80 dB. This response confirms the feasibility of the proposed resonator in very-high frequency applications such as IF band pass sections of RF front-end circuits. The filter consumes less than 5.5 mW from a 2.7 V supply and the measured dynamic range is 57 dB at IM3 of 0.5%, where the active area is 0.12 mm².     

A 2.4-GHz CMOS Monolithic VCO with an MOS Varactor

A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8m CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about –118 dBc/Hz at 1 MHz from the carrier.     

A Low-Voltage Low-Power Rail-to-Rail Constant g m Transconductance Amplifier

In this paper, a low-voltage low-power rail-to-rail constant g _m transconductance amplifier (TA) is introduced. The supply voltages are set at (±1.5 V). The circuit depends on selecting the maximum transconductance (g _m ) to achieve an almost constant g _m over the entire common-mode (CM) range. The circuit is then used to realize a second-order 4 MHz lowpass filter consuming 530 W, and a fifth-order 450 kHz lowpass elliptic filter consuming 2.3 mW. Both filters can be integrated on silicon without any external connections.     

Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultra-low supply voltage operation also in CMOS processes with high threshold voltages. This paper presents the theoretical basis for the design of V_T0n = | V_T0p | = 0.9VV_{T0n} = \left| {V_{T0p} } \right| = 0.9V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than ±18 A with a supply voltage down to 1 V, and relatively small device dimensions. In spite of the relatively large signal processing range, the class AB operation of the cell enabled a very low quiescent current consumption, 1 A in this design, resulting in a very high current efficiency and effective power consumption, as well as good noise performance.     

Design and implementation of a new four-quadrant MOS analog multiplier

A four-quadrant MOS analog multiplier is proposed using the quarter-square technique, which is based on the quadratic characteristics of an MOS transistor operating in the saturation region and the difference operation of four identical sourced-coupled differential amplifiers. The multiplier has a simple configuration and a large dynamic range over a wide frequency range, since each input signal passes only one transistor to reach the output. The operation of the multiplier was analyzed in detail, and the second-order effects were also analyzed. The proposed circuit was fabricated in 12-V p-well CMOS process with a 5-m minimum feature. The measured results show that linearity error is less than 1% for 5-V_p-p input at ±5 V supply voltage, and the-3 db bandwidth is 30 MHz.     

Continuous-Time 4th Order Butterworth Low-Pass Filter for Video Frequency Applications

In this paper, a continuous-time 4th order Butterworth low-pass filter based on current-mode processing is presented for applications over the video frequency range. A new type of integrator in which both voltage and currents may be integrated is presented and used as the main active block. The filter has been implemented using a very low-cost 2.4 m CMOS process (Mietec). The whole circuit occupies 2.8 mm² and consumes 19 mW from a ±1.5 V supply. Experimental results are given for a 4.5 MHz to 12 MHz tunable low-pass filter with 58 dB of dynamic range at 10 MHz.     

A Signal Conditioning Circuit for Piezoresistive Pressure Sensors With Variable Pulse-Rate Output

The equivalent impedance of the conventional ideal inductance implemented from two second-generation current conveyors is firstly calculated taking all the parasitic elements into account. Its equivalent electrical schema, which comprises six components is characterized. It is demonstrated that the most important deviation at high frequencies comes from the phase shifts of the transfers of the conveyors. Compensation of these effects are obtained from the first-order compensation method using a single additive resistor. SPICE simulations using an industrial BiCMOS process are used to demonstrate the validity of this approach. As an example, the current conveyors being DC biased with I₀ = 100 A and supplied under ±2.5 V, an inductance of 0.67 H was found directly usable without compensation up to about 15 MHz. This frequency range is then extended up to about 100 MHz when the circuit has been compensated from a single resistor of 75 .     

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design

Lowering supply voltage,V _DD, is the most effective means to reduce power dissipation of CMOS LSI design. In lowV _DD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage,V _th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to lowV _th, while the second approach degrades worst case circuit speed caused byV _th fluctuation in lowV _DD. This paper presents two circuit techniques to solve these problems, in both of whichV _th is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raisesV _th in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reducesV _th fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 VV _DD.     

Evaluation of MOS structures processed on 4H–SiC layers grown by PVT epitaxy

MOS capacitors have been fabricated on 4H–SiC epilayers grown by physical vapor transport (PVT) epitaxy. The properties were compared with those on similar structures based on chemical vapor deposition (CVD) layers. Capacitance–voltage (C–V) and conductance measurements (G–V) were performed in the frequency range of 1 kHz to 1 MHz and also at temperatures up to 475 K. Detailed investigations of the PVT structures indicate a stable behaviour of the interface traps from room temperature up to 475 K. The amount of positive oxide charge Q_O is 6.83 × 10⁹ cm⁻² at room temperature and decreases with temperature increase. This suggests that the processed devices are temperature stable. The density of interface states D_it obtained by Nicollian–Brews conductance method is lower in the structure based on the PVT grown sample.     

High Performance CMOS Analog Arithmetic Circuits

Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V₁ + V₂), subtraction (V₂ – V₁), add/invert –(V₁ + V₂), and multiply (V₁ × V₂). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 m CMOS technology.