Influence of optical properties of the SOI structure on the wafer temperature during rapid thermal annealing

Optical characteristics are compared theoretically, and temperature differences of the Si wafer with the B-doped SOI structure and substrate wafer are evaluated during rapid thermal annealing. It is shown that under identical annealing conditions and temperatures above 800 K, the difference in their temperatures can reach ∼30 K. We studied the dependence of the total emissivity and temperature of the wafer with the SOI structure on the concentration of the doping impurity in the Si layer. The method of the quantitative analysis of variations of the wafer temperature under invariable annealing conditions depending on the variations of emissivity of its surfaces is suggested.     

线切割机加工半导体晶片质量控制的研究

根据线切割机的工作原理,切片过程中硅片因机械作用造成的刀痕、损伤、破损产生包括机械应力和热应力在内的应力,进而产生滑移位错.当机械应力和热应力在高温处理过程中的作用超过晶体滑移临界应力时,会产生硅片的破碎.对于翘曲度、弯曲度、总厚度误差、中心厚度误差等方面的质量控制,通过调整线张力、进给速度、冷却剂流量等一系列工艺措施可达到目的及要求,大大降低了生产成本,提高了生产效率.实验证明,线切割机切出的硅片的厚度和质量都很好地满足了下一道工序的要求.     

Si/GaAs晶圆片键合热应力及其影响因素分析

分别利用Suhir双金属带热应力分布理论和有限元法研究了Si/GaAs晶圆片键合界面在退火过程中的热应力分布,并将热应力分布理论计算结果与有限元分析结果进行了对比验证,得到了一致的结论.根据计算分析结果,对晶圆片进行了结构热变形分析,并研究了不同因素对键合热应力的影响,提出了减小键合热应力的有效措施.     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.     

Surface activation using oxygen and nitrogen radical for Ge-Si Avalanche photodiode integration

In this work, an alternative method for producing the single crystalline Ge-Si Avalanche photodiodes (APD) with low thermal budget was investigated. Structural and electrical investigations show that low temperature Ge to Si wafer bonding can be used to achieve successful APD integration. Based on the surface chemistry of the Ge layer, the buried interfaces were investigated using high resolution transmission electron microscopy as a function of surface activation after low temperature annealing at 200 and 300 °C. The hetero-interface was characterized by measuring forward and reverse currents.     

HgCdTe/Si materials for long wavelength infrared detectors

The heteroepitaxial growth of HgCdTe on large-area Si substrates is an enabling technology leading to the production of low-cost, large-format infrared focal plane arrays (FPAs). This approach will allow HgCdTe FPA technology to be scaled beyond the limitations of bulk CdZnTe substrates. We have already achieved excellent mid-wavelength infrared (MWIR) and short wavelength infrared (SWIR) detector and FPA results using HgCdTe grown on 4-in. Si substrates using molecular beam epitaxy (MBE), and this work was focused on extending these results into the long wavelength infrared (LWIR) spectral regime. A series of nine p-on-n LWIR HgCdTe double-layer heterojunction (DLHJ) detector structures were grown on 4-in. Si substrates. The HgCdTe composition uniformity was very good over the entire 4-in. wafer with a typical maximum nonuniformity of 2.2% at the very edge of the wafer; run-to-run composition reproducibility, realized with real-time feedback control using spectroscopic ellipsometry, was also very good. Both secondary ion mass spectrometry (SIMS) and Hall-effect measurements showed well-behaved doping and majority carrier properties, respectively. Preliminary detector results were promising for this initial work and good broad-band spectral response was demonstrated; 61% quantum efficiency was measured, which is very good compared to a maximum allowed value of 70% for a non-antireflection-coated Si surface. The R₀A products for HgCdTe/Si detectors in the 9.6-μm and 12-μm cutoff range were at least one order of magnitude below typical results for detectors fabricated on bulk CdZnTe substrates. This lower performance was attributed to an elevated dislocation density, which is in the mid-10⁶ cm⁻² range. The dislocation density in HgCdTe/Si needs to be reduced to <10⁶ cm⁻² to make high-performance LWIR detectors, and multiple approaches are being tried across the infrared community to achieve this result because the technological payoff is significant.     

界面热应力对InP/Si键合质量的影响

通过实验和理论计算,分析了InP/Si键合过程中,界面热应力的分布情况、影响键合结果的关键应力因素及退火温度的允许范围。分析结果表明,由剪切应力和晶片弯矩决定的界面正应力是晶片中心区域大面积键合失败的主要原因,为保证良好的键合质量,InP/Si键合退火温度应该在300～350℃范围内选取。具体实验验证表明,该理论计算值与实验结果相一致。最后,在300℃退火条件下,很好地实现了2inInP/Si晶片键合,红外图像显示,界面几乎没有空洞和裂隙存在,有效键合面积超过90%。     

Atomically Smooth Graphene-Based Hybrid Template for the Epitaxial Growth of Organic Semiconductor Crystals

Atomically thin 2D materials are good templates to grow organic semiconductor thin films with desirable features. However, the 2D materials typically exhibit surface roughness and spatial charge inhomogeneity due to nonuniform doping, which can affect the uniform assembly of organic thin films on the 2D materials. A hybrid template is presented for preparation of highly crystalline small-molecule organic semiconductor thin film that is fabricated by transferring graphene onto a highly ordered self-assembled monolayer. This hybrid graphene template has low surface roughness and spatially uniform doping, and it yields highly crystalline fullerene thin films with grain sizes >300 nm, which is the largest reported grain size for C₆₀ thin films on 2D materials. A graphene/fullerene/pentacene phototransistor fabricated directly on the hybrid template has five times higher photoresponsivity than a phototransistor fabricated on a conventional graphene template supported by a SiO₂ wafer.     

X射线光刻掩模背面刻蚀过程中的形变仿真

开发了理论模型以验证有限元方法用于X射线光刻掩模刻蚀过程数值仿真的正确性。利用相同的有限元技术，对X射线光刻掩模的背面开窗、Si片刻蚀过程进行数值仿真。结果表明，图形区域的最大平面内形变(IPD)出现在上、下边缘处，最大非平面形变(OPD)出现在左、右边缘处。此外对Si片单载荷步刻蚀和多载荷步刻蚀的仿真进行比较，结果表明图形区域最终的形变量与Si片刻蚀的过程无关。     

Thermal uniformity of 12-in silicon wafer in linearlyramped-temperature transient rapid thermal processing

This paper presents a systematic method for estimating the dynamic incident-heat-flux profiles required to achieve thermal uniformity in 12-in silicon wafers during linearly ramped-temperature transient rapid thermal processing using the inverse heat-transfer method. A two-dimensional thermal model and temperature-dependent silicon wafer thermal properties are adopted in this study. The results show that thermal nonuniformities on the wafer surfaces occur during ramped increases in direct proportion to the ramp-up rate. The maximum temperature differences in the present study are 0.835°C, 1.174°C, and 1.516°C, respectively, for linear 100°C/s, 200°C/s, and 300°C/s ramp-up rates. Although a linear ramp-up rate of 300°C/s was used and measurement errors did reach 3.864°C, the surface temperature was maintained within 1.6°C of the center of the wafer surface when the incident-heat-flux profiles were dynamically controlled according to the inverse-method approach. These thermal nonuniformities could be acceptable in rapid thermal processing systems     

1990 Electronic Materials Conference

Silicon doped epitaxial layers of InP have been prepared by low pressure metalorganic chemical vapour deposition, using disilane as the source of silicon. Trimethylindium and phosphine were used as the source reactants for the growth. The doping characteristics for the epitaxial growth were investigated at substrate temperatures in the range 525–750° C and for doping levels in the range 4 × 10¹⁶−2 × 10¹⁹ cm⁻³. The results indicated that the Si doping level is proportional to the disilane flow rate. The Si incorporation rate increases with temperature, but becomes temperature-independent forT > 620° C. Comparison between Si concentrations determined by Secondary Ion Mass Spectroscopy, donor levels determined by Hall effect measurements, and optical measurements at 7 K indicates that approximately 50% of the Si in the InP is in the form of electrically inactive species. Uniform doping over 5 cm wafer dimensions has been obtained for growth atT = 625° C.     

用于制备SOI材料的基于硅片键合和双层多孔硅剥离的薄外延硅膜转移技术

采用在阳极化反应时改变电流强度的办法 ,在高掺杂的 P型硅 (111)衬底上制备了具有不同多孔度的双层结构多孔硅层 .用超高真空电子束蒸发技术在多孔硅表面外延生长了一层高质量的单晶硅膜 .在室温下 ,该外延硅片同另一生长有热二氧化硅的硅片键合在一起 ,在随后的热处理过程中 ,键合对可在多孔硅处裂开 ,从而使外延的单晶硅膜转移到具有二氧化硅的衬底上以形成 SOI结构 .扫描电镜、剖面投射电镜、扩展电阻和霍尔测试表明 SOI样品具有较好的结构和电学性能     

An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Silicon template fabrication for imprint process with good demolding characteristics

Demolding force for thermal imprint process to polymethylmethacrylate (PMMA) film is examined by use of Si templates with various side wall profiles. Patterns with tapered side wall profile can be fabricated by control of etching conditions. Side wall profile can be smoothened by anisotropic etching by use of mixed solution of potassium hydroxide (KOH) solution and isopropyl-alcohol. It is confirmed that demolding force can be reduced when mold with tapered side wall pattern is used. Demolding force can be greatly reduced by KOH treatment. Especially, when the template with taper and smooth side wall patterns is used, demolding force is below our measurement system limit of 0.1 kgf. It is confirmed that the KOH treatment is very effective in order to reduce demolding force.     

直接键合四结GaAs太阳电池研究

晶圆直接键合技术由于能将表面洁净的两个晶圆集成到一起,从而可以用来制备晶格失配 III-V族多结太阳电池。为了制备GaInP/GaAs/InGaAsP/InGaAs四结太阳电池,需采用具有低电阻率的GaAs/InP键合界面,从而实现GaInP/GaAs和InGaAsP/InGaA上下两个子电池的电学导通。我们设计并研究了具有不同掺杂元素和掺杂浓度的三种键合界面,并采用IV曲线对其电学性质进行表征。此外,对影响键合界面质量的关键工艺过程进行了研究,主要包括表面清洗技术和键合参数优化,例如键合温度、键合压力和键合时间等。最终制备出的键合四结GaInP/GaAs/InGaAsP/InGaAs太阳电池在AM0条件下效率最高达33.2%。     

Wafer‐Level Self‐Organized Copolymer Templates for Nanolithography with Sub‐50 nm Feature and Spatial Resolutions

Robust lithographic templates, with sub‐50 nm feature and spatial resolutions, that exhibit high patterning integrity across a full‐wafer are demonstrated using self‐organized copolymer reverse micelles on 100 mm Si wafers. A variation of less than 5% in the feature size and periodicity of polymeric templates across the entire wafer is achieved simply by controlling the spin‐coating process. Lithographic pattern transfer using these templates yields Si nanopillar arrays spanning the entire wafer surface and exhibiting high uniformity inherited from the original templates. The variation in geometric characteristics of the pillar arrays across the full‐wafer surface is validated to be less than 5% using reflectance spectroscopy. The physical basis of the change in reflectance with respect to sub‐10 nm variations in geometric parameters of pillar arrays is shown by theoretical modelling and simulations. Successful fabrication of highly durable TiO₂ masks for nanolithography with sub‐50 nm feature width and spatial resolutions is achieved through highly controlled vapour phase processing of reverse micelle templates. This allows lithographic pattern‐transfer of organic templates with a feature thickness and separation of less than 10 nm, which is otherwise not possible through other approaches reported in literature.     

优化主氢流量及C/Si比提高76.2mm4H-SiC同质外延浓度均匀性

源在外延片直径方向上的耗尽导致了外延片上局部各点的生长速率及掺杂浓度是个随位置变化的量,因此造成了外延片厚度及浓度的不均匀性.通过引入基座气浮旋转可以有效降低这种不均匀性,在典型工艺条件下,采用基座旋转,76.2 mm 4H-SiC外延片厚度不均匀性、p型掺杂浓度不均匀性和n型掺杂不均匀性分别为0.21%、1.13%和...     

Advanced development process for ultrafine photoresist patterns

Addition of appropriate surfactant to developer will improve wettability of the developer, thus promoting uniformity of dissolution of exposed photoresist. Surface smoothness of the Si substrate is also improved when developer contains surfactant. The only disadvantage is that surfactant is adsorbed onto the wafer surface; however, it can be removed by a Pt-H₂O₂ treatment without degrading the photoresist pattern. The optimal tetramethylammonium hydroxide (TMAH) concentration in the developer was investigated by measuring the developing selectivity of the photoresist against various TMAH concentration levels. The developing selectivity is considered to directly affect the photoresist profile and resolution in the development process