Yield optimization in wafer scale circuits with hierarchical redundancies

For wafer scale integration, the concept of redundancy is important to yield enhancement and circuit repairability. In designing today's complex VLSI circuits, structured hierarchical design methodology in which a chip is partitioned into different levels of building blocks is generally preferred. The question naturally arises: Can hierarchy of redundancies be used to advantage? To maximize the circuit yield, we are therefore concerned with the size of the block at each level and the distribution of redundancies among blocks. This paper analyses the relationship between yield and the redundancy distribution for a two-level chip architecture with a given over-all redundancy overhead factor.     

Biopolymer Nanoscale Assemblies as Building Blocks for New Materials: A Review

Biopolymers, a class of fascinating polymers from biomass provide sustainability, biodegradability, availability, biocompatibility, and unique properties. A ubiquitous feature of biopolymers is their hierarchical structure, with the presence of well-organized structures from the nanoscale to macroscopic dimensions. This structural organization endows biopolymers with toughness, defect resistance, and bucking adaptability. To retain these inherent structural features, nano-structural assemblies isolated from biomass have been applied as building blocks to construct new biopolymer-based materials. This top-down processing strategy is distinct from the more traditional molecular-level bottom-up design and assembly approach for new materials. In this review, the hierarchical structures of several representative biopolymers (cellulose, chitin, silk, collagen) are introduced with a focus on these nanoscale building blocks, as well as highlighting the similarities and differences in the respective chemistries and structures. Recent progress in production strategies of these natural building blocks are summarized, covering methods and treatments used for isolations. Finally, approaches and emerging applications of biopolymer-based materials using these natural nano- and meso-scale building blocks are demonstrated in areas of biomedicine, electronics, environmental, packaging, sensing, foods, and cosmetics.     

Hierarchical Nanocomposites Derived from Nanocarbons and Layered Double Hydroxides ‐ Properties,Synthesis, and Applications

The combination of one‐dimensional and two‐dimensional building blocks leads to the formation of hierarchical composites that can take full advantages of each kind of material, which is an effective way for the preparation of multifunctional materials with extraordinary properties. Among various building blocks, nanocarbons (e.g., carbon nanotubes and graphene) and layered double hydroxides (LDHs) are two of the most powerful materials that have been widely used in human life. This Feature Article presents a state‐of‐the‐art review of hierarchical nanocomposites derived from nanocarbons and LDHs. The properties of nanocarbons, LDHs, as well as the combined nanocomposites, are described first. Then, efficient and effective fabrication methods for the hierarchical nanocomposites, including the reassembly of nanocarbons and LDHs, formation of LDHs on nanocarbons, and formation of nanocarbons on LDHs, are presented. The as‐obtained nanocomposites derived form nanocarbons and LDHs exhibited excellent performance as multifunctional materials for their promising applications in energy storage, nanocomposites, catalysis, environmental protection, and drug delivery. The fabrication of LDH/carbon nanocomposites provides a novel method for the development of novel multifunctional nanocomposites based on the existing nanomaterials. However, knowledge of their assembly mechanism, robust and precise route for LDH/nanocarbon hybrid with well designed structure, and the relationship between structure, properties, and applications are still inadequate. A multidisciplinary approach from the scope of materials, physics, chemistry, engineering, and other application areas, is highly required for the development of this advanced functional composite materials.     

Smooth side-match weighted vector quantiser with variable block size for image coding

Although side-match vector quantisation (SMVQ) reduces the bit rate, the quality of image coding using SMVQ generally degenerates as the grey level transition across the boundaries of neighbouring blocks increases or decreases. The author proposes a smooth side-match weighted method to yield a state codebook according to the smoothness of the grey levels between neighbouring blocks. When a block is encoded, a corresponding weight is assigned to each neighbouring block to represent its relative importance. This smooth side-match weighted vector quantisation (SSMWVQ) achieves a higher PSNR than SMVQ at the same bit rate. Also, each block can be pre-encoded in an image, allowing each encoded block to use all neighbouring blocks to yield the state codebook in SSMWVQ, rather than using only two neighbouring blocks, as in SMVQ. Moreover, SSMWVQ selects many high-detail blocks as basic blocks to enhance the coding quality, and merges many low-detail blocks into a larger one to reduce further the bit rate. Experimental results reveal that SSMWVQ has a higher PSNR and lower bit rate than other methods.     

High-level parameterizable area estimation modeling for ASIC designs

Architectural design space exploration and early area budgeting for ASIC and IP block development require accurate high level gate count estimation methods without requiring the hardware being fully specified. The proposed method uses hierarchical and parameterizable models requiring minimal amount of information about the implementation technology to meet this goal. The modeling process flow is to: (1) create a block diagram of the design, (2) create a model for each block, and (3) sum up estimates of all sub-blocks by supplying the correct parameters to each sub-model. We discuss the model creation for a few parameterized library blocks as well as three communication blocks and a processor core from real IC projects ranging from 22 to 250 kgates. The average relative estimation error of the proposed method for the library blocks is 3.2% and for the real world examples 4.0%. The best application of this method is early in the design phase when different implementation architectures are compared.     

Nanoelectronic content-addressable memory

A novel nanoelectronic single-electron content addressable memory is designed and simulated. The proposed memory has three important building blocks: a storage block, a comparison block and an addressing block. These building blocks were built based on single-electron circuits such as Reset-Set latches, exclusive-or gates and a WTA neural network. Each one of the building blocks was separately adjusted to provide room temperature operation before being connected together. Some analyses concerning stability of each block and of the whole memory circuit were made. The nanoelectronic memory was successfully validated by simulation.     

基于优化的、层次式的数/模转换器自动综合

本文介绍了一种基于优化的、层次式的Ｄ／Ａ转换器自动综合方法,该方法根据 本性能要求首先确定对各单元电路的性能要求,再由这些性能要求驱动相应的单元电路综合模块进行单元电路的综合。最后采用一个自下而上的过程难证所产生的Ｄ／Ａ转换器的性能,在两个综合欠上,利用多维下降单纯形优化算法进行优化求解。     

一种基于小波纹理特征的目标检测方法

给出了一种利用小波分块分解和灰度共生矩阵特征来提取目标的方法。首先对图像进行分块小波变换,然后求分块灰度共生矩阵并且计算小波共生矩阵特征向量,选取纹理特征最大的作为种子区域;最后利用均值聚类的方法进行目标标记。实验结果证明,能够检测红外和可见光图像中各种类型的目标。     

Reliability Modeling Using SHARPE

Combinatorial models such as fault trees and reliability block diagrams are efficient for model specification and often efficient in their evaluation. But it is difficult, if not impossible, to allow for dependencies (such as repair dependency and near-coincident-fault type dependency), transient and intermittent faults, standby systems with warm spares, and so on. Markov models can capture such important system behavior, but the size of a Markov model can grow exponentially with the number of components in this system. This paper presents an approach for avoiding the large state space problem. The approach uses a hierarchical modeling technique for analyzing complex reliability models. It allows the flexibility of Markov models where necessary and retains the efficiency of combinatorial solution where possible. Based on this approach a computer program called SHARPE (Symbolic Hierarchical Automated Reliability and Performance Evaluator) has been written. The hierarchical modeling technique provides a very flexible mechanism for using decomposition and aggregation to model large systems; it allows for both combinatorial and Markov or semi-Markov submodels, and can analyze each model to produce a distribution function. The choice of the number of levels of models and the model types at each level is left up to the modeler. Component distribution functions can be any exponential polynomial whose range is between zero and one. Examples show how combinations of models can be used to evaluate the reliability and availability of large systems using SHARPE.     

Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces

Analog and Mixed Signal (AMS) designs can be formally modeled as hybrid systems [45] and therefore formal verification techniques applicable to hybrid systems can be deployed to verify them. An extension to a formal verification approach applicable to hybrid systems is proposed to verify AMS designs [31]. In this approach formal verification (FV) is carried out on an AMS block using simulation traces from SPICE, a simulator widely used in the design and verification of analog and AMS blocks. A broader implication of this approach is the ability to carry out hierarchical verification using relevant simulation traces obtained at different abstraction levels of a design when modeled in appropriate platforms. This enables a seamless transition of design and verification artifacts from the highest level of abstraction to the lowest level of implementation at the transistor level of any AMS design and a resulting increase in confidence on the correctness of the final implementation. The proposed approach has been justified with its applications to different AMS design blocks. For each design, its formal model and the proposed computational techniques have been incorporated into CheckMate [11] - a FV tool for hybrid systems based on MATLAB and the Simulink/Stateflow framework from MathWorks. A further justification of the proposed approach is the resulting improvements observed in terms of reduced verification time for different specifications in each design.     

FPCS——一种适用于积木块方式的布局及平面规划系统

本文简述了一种分级式的自下而上结群和自上而下分划定位相结合的全定制方式的积木块(building block)布局及平面规划(floorplanning)系统.本方法基于积木块的尺寸、形状、连接状况、引线位置以及芯片引线端等的要求逐级优化组合若干种积木块组,并且根据工艺条件进行了布线区面积估计,以便得到较好的布局结果.如果积木块的尺寸或其长宽比可以改变,则本系统可改变其尺寸及形状从而优化布局结果.由于采用了多种有效的实用方法,并把它们有机地统一在系统中,因此使布局能在基本满足用户要求的条件下,做到和布线结果基本匹配.实验结果表明,这种方法是令人满意的.     

Analogue neural networks with distributed neurons

A new technique is proposed for implementing neurons in analogue electronic neural networks. It features integrating a fraction of a neuron with each synapse. Each neuron is distributed over all associated synapses. This methodology operates with just one building block, the distributed-neutron synapse, in contrast to existing techniques which are based on two distinct blocks, the neuron and synapse. This approach can be applied to a variety of implementations, including transconductor and MOSFET-op-amp neural networks. Modularity, ease of interconnectivity, expandability and reconfigurability are the advantages of this technique.<>     

Chameleon: a dual-mode 802.11b/Bluetooth receiver system design

In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-/spl mu/m BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.     

Edge oriented block motion estimation for video coding

Intensity-based block motion estimation and compensation algorithms are widely used to exploit temporal redundancies in video coding, although they suffer from several drawbacks. One of the problems is that blocks located on boundaries of moving objects are not estimated accurately. It causes poor motion-compensated prediction along the moving edges to which the human visual system is very sensitive. By considering the characteristics of block motions for typical image sequences, an intelligent classifier is proposed to separate blocks containing moving edges to improve on conventional intensity-based block matching approaches. The motion vectors of these blocks are computed using edge matching techniques, so that the motion-compensated frames are tied more closely to the physical features. The proposed method can then make use of this accurate motion information for edge blocks to compute the remaining non-edged blocks. Consequently, a fast and efficient block motion estimation algorithm is developed. Experimental results show that this approach gives a significant improvement in accuracy for motion-compensated frames and computational complexity, in comparison with the traditional intensity-based block motion estimation methods     

Mixed microwave-digital and multi-rate approach for wideband beamforming applications using 2-D IIR beam filters and nested uniform linear arrays

The presented work explores novel methods for synthesizing approximately frequency independent array factors at lower hardware complexity for wideband beamforming applications. The proposed approach employs 2-D infinite impulse response (IIR) digital beam filters together with nested uniform linear arrays (ULAs). The array is designed to have multiple levels of nesting. Each level of nesting consists of a ULA covering a temporal subband of the incident wideband signal. The use of nested arrays provides the required aperture size using a smaller number of elements compared to using a single ULA to capture the entire wideband signal. The use of different levels of nesting allows the operation of the digital processor for each sub-band at different clock rates. This is a hierarchical approach that saves both digital VLSI hardware and power consumption. The 2-D IIR digital beam filters that process each subband signal from each of the nested subarray achieves wideband beamforming. Simulations illustrate approximately frequency independent passbands as required in wideband beamforming.     

A universal building block for advanced modular design of microwave filters

A universal building block for modular design of microwave filters is introduced. The second order block contains two resonators which are not coupled to each other. By adjusting the strengths and signs of its coupling coefficients, the block can be used to design bandpass, bandstop and linear-phase filters. For bandpass filters, Chebychev as well as symmetric and asymmetric pseudo-elliptic responses with one or two finite transmission zeros can be designed. For linear-phase filters, two finite transmission zeros can placed practically anywhere in the complex plane as long as the realizability condition is met. Bandstop filters with no finite reflection zeros as well as symmetric and asymmetric pseudo-elliptic responses with one or two finite reflection zeros can be achieved by the same building block. The block is so flexible it can even generate bandstop responses with complex finite reflection zeros for group delay control. Higher order filters are designed modularly by cascading the appropriate number of building blocks. Coupling matrices of a number of cases are presented to demonstrate the flexibility and the universality of the building block.     

Modular analysis and design of log-domain circuits based on LIN↔ELIN transformations

We systematized and developed some procedures for the modular design of externally-linear internally nonlinear (ELIN) circuits resulting in a general LIN↔ELIN transformation procedure. This one was also extended to analysis of these types of circuits. The procedure is exemplified on log-domain circuits. In the design one starts with the linear block diagram (LIN) described by transfer functions and one substitutes directly each linear building block by a corresponding nonlinear one. The parameters of each nonlinear component depend on the given parameters of its linear correspondent. Input F ⁻¹ and output F blocks are added. In the analysis one identifies the nonlinear basic circuit components and each of them is substituted by its corresponding linear building block. Input and output F ⁻¹-F cells are removed. The ideal transfer function can be calculated on the linear block diagram now. The LIN↔ELIN transformations make a direct connection between equivalent linear and ELIN circuits, simplify their design and analysis procedures and permit the development of CAD procedures.     

SPW中自定义模块的创建与测试

SPW是一个先进的通信系统建模、仿真工具，它具有丰富的通信仿真模块和非常灵活的创建自定义模块功能。通过创建一个简单的自定义模块并对其进行功能测试，介绍了在SPW中创建及测试用户自定义模块的方法。这一实例表明，在SPW中可以将现成的模块与用户自定义模块有机结合在一起，从而大大提高了工程人员的工作效率，同时又扩展了SPW的应用领域。     

总线事务级验证模型仿真性能研究

系统芯片的功能验证一直是芯片设计中最具挑战性的部分。基于事务的验证方法学被用来解决功能验证中的困难。该方法学通过提高验证的抽象层次来降低验证复杂度。但同时也对使用该方法学构建的验证平台组件可重用性有了更高的要求。其中总线功能模型可以在验证中模拟设计中的其他模块,是构建验证平台的重要组件。本文在方法学的基础上,讨论了两种类型的总线功能模型,并给出了verilog硬件描述语言的实现模型,最后通过实验比较了两种总线功能模型的仿真性能。     

On the use of high-impedance power supplies to reduce the substrate switching noise in system-on-chips

This paper analyzes the generation and the propagation in system-on-chips of the switching noise due to embedded core logic blocks. Such disturbances contribute to degrade the performance of the other on-chip circuits and cause unwanted electromagnetic emission. These parasitic effects can be largely ascribed to the steep currents that flow into the power supply interconnects of the core logic blocks and to the parasitic coupling of the system-on-chip building blocks through the silicon substrate they share.In this work it is shown that the substrate voltage bounce due to the switching noise can be significantly attenuated if conventional low-impedance DC power supplies are replaced by high-impedance one. The effectiveness of the proposed approach is validated through computer simulations and experimental tests carried out on the digital core block of a test chip.