共漏极双功率MOSFET封装研究

针对适用于锂电池保护电路特点要求的共漏极功率MOSFET的封装结构进行了研发和展望.从传统的TSSOP-8发展到替代改进型SOT-26,一直到芯片级尺寸的微型封装外形,其封装效率越来越高,接近100%.同时,在微互连和封装结构的改进方面,逐渐向短引线或焊球无引线、平坦式引脚、超薄型封装和漏极焊盘散热片暴露的方向发展,增...     

理解功率MOSFET的电流

通常,在功率MOSFET的数据表中的第一页,列出了连续漏极电流ID,脉冲漏极电流IDM,雪崩电流IAV的额定值,然后对于许多电子工程师来说,他们对于这些电流值的定义以及在实际的设计过程中,它们如何影响系统以及如何选取这些电流值,常常感到困惑不解,本文将系统的阐述这些问题,并说明了在实际的应用过程中如何考虑这些因素,最后给出了选取它们的原则。     

三维功率MOSFET器件的热可靠性设计

基于三维集成技术的功率MOSFET器件,在发热量大和散热难的双重压力下,热可靠性设计凸显得尤为重要。文中采用硅通孔散热方式,在三维功率器件内嵌入大量的散热硅通孔,以降低芯片内热阻,疏导功率器件产生的热量,保证器件有源区结温低于极限安全结温,可有效提高芯片的热可靠性。以100 V,60 A的功率VDMOS器件为研究对象,以提高芯片的热可靠性为目的,合理设计和充分优化了三维功率MOSFET器件的版图和散热硅通孔的布局。基于多物理场分析软件开展了大量的热可靠性仿真分析工作,并流片验证了设计的正确性。     

使用MOSFET管不同参数影响研究

总结MOSFET管分类及特点及MOSFET管的温度对开启电压,导通电阻,漏源极电压,漏电流,雪崩能量等参数的影响。     

CMOS IC漏极静态电流测试技术的现状与发展

全面介绍了CMOS集成电路漏极静态电流(IDDQ)测试技术的现状、应用及其发展趋势。与其它主要用于检测逻辑功能的测试技术不同，IDDQ主要用于检测电路的物理缺陷和工艺故障。作为逻辑功能测试的重要补充，IDDQ技术可提高集成电路的可测性和故障覆盖率，保证集成电路的可靠性。     

SiZ710DT:功率MOSFET

Vishay推出采用PowerPAIR 6 mm×3.7 mm封装和TrenchFET GenⅢ技术的非对称双通道TrenchFET功率MOSFET——SiZ710DT,新器件比其前一代器件的导通电阻减小43%,同时具有更高的最大电流并提高效率。SiZ710DT在一个小尺寸封装中整合了低边和高边MOSFET,导通电阻低。SiZ710DT的低边Channel 2 MOSFET利用了非对称结构在优化空间上的     

Vishay推出新型TrenchFET功率MOSFET

日前．Vishay宣布推出新型20V和30V p-通道TrenchFET功率MOSFET-Si7633DP和Si7135DP。这次推出的器件采用SO-8封装，具有±20V栅源极电压以及业内最低的导通电阻。     

飞兆推出最小尺寸MOSFET器件，持续电流突破1A

飞兆半导体公司(Fairchild Semiconductor)推出最小尺寸的互补对称MOSFET器件——FDC6020C，为微型“点”功率应用和负载点(POL)DC／DC开关转换器设计提供高于1A的持续电流。该器件将两个NOSFET集成在一个超小型的SuperSOT-6FLMP封装(倒装导模封装)中。     

国际整流器公司针对锂离子电池保护推出全新功率MOSFET

<正>全球功率半导体和管理方案领先供应商国际整流器公司(International Rectifier,简称IR)近日针对锂离子电池保护应用推出配备IR最新低压MOSFET硅技术的一系列器件,包括IRL6297SD双N通道Direct FET MOSFET。全新功率MOSFET具有极低的导通电阻,可大幅减少导通损耗。产品可作为N通道及P通道配置的20     

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.     

Ionising radiation effects on MOSFET drain current

We have investigated the radiation effect on MOSFET performances due to the incidence of a few ions in the gate area. We present new experimental evidence that a single ion may lead to the MOSFET drain current collapse, due to the formation of a localized oxide damaged region over a large portion of the channel width, well before the breakdown onset. We call these phenomena single event drain current collapse (SEDC²). This effect is evident in devices with small channel width (W), i.e., comparable to the size of damaged region, and fades as W increases over the size of the ion damaged region.     

Influence of dielectric breakdown on MOSFET drain current

Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m.     

基于MOSFET漏电流温度特性的室温红外探测器

基于MOSFET的漏电流温度特性，提出了一种可与CMOS工艺兼容的新型室温红外探测器。它采用在SOI衬底上实现的MOSFET作为探测红外灵敏元，在MOSFET的钝化层上制作可提高红外吸收率的光学谐振腔，并利用硅微机械加工技术将SOI的隐埋氧化层悬空，形成热绝缘微桥结构。MOSFET在担当探测红外辐射灵敏元的同时，又作为放大处理电路的一部分，简化了电路。分析表明，探测器的探测率可高达10^9-10^10cmHz^1/2W^-1.     

Modeling of the MOSFET inversion charge and drain current, inmoderate inversion

The widespread use of MOS technology in analog circuit design demands a precise and efficient circuit simulation model of the MOS transistor valid in all regions of inversion. Currently available circuit simulation models fail in the intermediate range of gate voltages, known as the moderate inversion region. Expressions characterizing the large-signal behavior of the long-channel MOS transistor in the moderate inversion region are derived. The correct dependencies on all the physical and process parameters are preserved by a careful approximation to the physical equations, based on the charge sheet assumption. Another goal is to develop expressions that treat the moderate inversion as a small, voltage-dependent correction to currently existing simplified models. This approach should allow a simple modification of the existing circuit simulation models to improve the accuracy in moderate inversion. The model was compared with a numerical charge sheet model and with experimental measurements of a long-channel, ion-implanted NMOS transistor. The expressions could serve as a basis for a comprehensive MOSFET circuit simulation model     

Suppression of drain source ringing in 100 kHz MOSFET induction heating power supply

The letter is concerned with a full bridge, current-fed MOSFET inverter feeding a parallel resonant induction heating load. A means of suppressing ringing between parasitic lead inductance and drain source capacitance is described.     

An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET

In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L₁/L₂ ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement.     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.