混合PiN/Schottky二极管的研究

对混合PiN/Schottky二极管（MPS）进行研究,首先对MPS二极管的工作原理进行了分析,通过对MPS二极管、肖特基二极管、PIN二极管的伏安特性进行模拟,结果表明MPS二极管正向压降小,电流密度大,反向漏电流小,是一种具有肖特基正向特性和PN结反向特性的新型整流器。可以通过改变肖特基和PN结的面积比来调整MPS二极管的性能,与肖特基二极管和PIN二极管相比具有明显的优势,是功率系统不可或缺的功率整流管。     

隧道二极管的应用

隧道二极管简称隧道管,是用锗、砷化镓、锑化镓等半导体材料制造的一种小型二极管.它的结构特点是有一个两边重掺杂的PN结,因而有一个很窄的势垒区.因此,在隧道管两端加上一个很小的偏置电压,无论正向或反向都会出现由电子穿透势垒的隧道效应而产生的隧道电流,从而使它具有与一般PN结二极     

10A/600V大功率硅基JBS肖特基二极管的制备

为了弥补传统肖特基二极管漏电流大和反向耐压低的不足,采用栅条P+-N结和肖特基结嵌套形成结势垒肖特基二极管(JBS),终端结构由7道场限环和1道切断环构成。通过模拟确定最优参数后流片试验,同步制备肖特基二极管(SBD)和Pi N二极管作为对比。结果表明:制备的JBS二极管兼备SBD二极管正偏和Pi N二极管反偏的优点。在漏电流密度小于1×10-5A/cm2时,反向耐压达到600 V;正向电流10 A(80.6 A/cm2)时,导通压降仅为1.1V。     

凹栅槽AlGaN/GaN HEMTs器件退火处理效应

研究了如何减小等离子体干法刻蚀导致的大肖特基漏电. 用X射线光电能谱（XPS）分析刻蚀前后的AlGaN表面,发现刻蚀后AlGaN表面出现了N空位,导致肖特基栅电流偏离热电子散射模型,N空位做为一种缺陷使得肖特基结的隧穿几率增大,反向漏电增大,肖特基势垒降低. 介绍了一种AlGaN/GaN HEMTs器件退火处理方法,优化退火条件为400℃, N2氛围退火10min. 退火后,栅金属中的Ni与Ga原子反应从而减少N空穴造成的缺陷,器件肖特基反向漏电减小三个量级,正向开启电压升高,理想因子从3.07降低到了2.08.     

凹栅槽AlGaN/GaN HEMTs器件退火处理效应

研究了如何减小等离子体干法刻蚀导致的大肖特基漏电.用X射线光电能谱(XPS)分析刻蚀前后的AlGaN表面,发现刻蚀后AlGaN表面出现了N窄位,导致肖特基栅电流偏离热电子散射模型,N空位做为一种缺陷使得肖特基结的隧穿几率增大,反向漏电增大,肖特基势垒降低.介绍了一种AlGaN/GaN HEMTs器件退火处理方法,优化退火条件为400℃,Nz氛围退火10min.退火后,栅金属中的Ni与Ga原子反应从而减少N空穴造成的缺陷,器件肖特基反向漏电减小三个量级,正向开启电压升高,理想因子从3.07降低到了2.08.     

2700V4H-SiC结势垒肖特基二极管

在76.2 mm 4H-SiC晶圆上采用厚外延技术和器件制作工艺研制的结势垒肖特基二极管(JBS).在室温下,器件反向耐压达到2700 V.正向开启电压为0.8V,在VF=2V时正向电流密度122 A/cm2,比导通电阻Ron=8.8 mΩ·cm2.得到肖特基接触势垒qφв=1.24 eV,理想因子n=1.     

6H-SiC高压肖特基势垒二极管

在可商业获得的 N型 6 H - Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ,在此结构材料上 ,通过热蒸发 ,制作 Ni/6 H- Si C肖特基势垒二极管 .测量并分析了肖特基二极管的电学特性 ,结果表明 ,肖特基二极管具有较好的整流特性 :反向击穿电压约为 45 0 V,室温下 ,反向电压 VR=- 2 0 0 V时 ,反向漏电流 JL=5× 10 - 4 A· cm- 2 ;理想因子为 1.0 9,肖特基势垒高度为 1.2 4— 1.2 6 e V ,开启电压约为 0 .8V     

3300 V-10 A SiC肖特基二极管北大核心CSCD

利用一次离子注入同时形成有源区和结终端结构,实现3 300 V 4H-SiC肖特基二极管。器件的正向电压为1.7 V时,电流达到10.3 A,相应电流密度为100 A/cm2,比导通电阻为7.77 mΩ·cm2。在3 300 V反向偏置电压下反向漏电流为226μA。测试同一晶圆上的pn二极管显示,设计的场限环结终端击穿电压可以达到4 000 V,达到仿真结果的95%。分析发现肖特基二极管的漏电流主要由肖特基接触的热场电子发射产生,有源区的肖特基接触线宽直接影响器件的正向电流密度和反向漏电流。设计合适的肖特基接触宽度是实现高性能器件的关键。     

3300 V-10 A SiC肖特基二极管

利用一次离子注入同时形成有源区和结终端结构,实现3 300 V 4H-SiC肖特基二极管。器件的正向电压为1.7 V时,电流达到10.3 A,相应电流密度为100 A/cm2,比导通电阻为7.77 mΩ·cm2。在3 300 V反向偏置电压下反向漏电流为226μA。测试同一晶圆上的pn二极管显示,设计的场限环结终端击穿电压可以达到4 000 V,达到仿真结果的95%。分析发现肖特基二极管的漏电流主要由肖特基接触的热场电子发射产生,有源区的肖特基接触线宽直接影响器件的正向电流密度和反向漏电流。设计合适的肖特基接触宽度是实现高性能器件的关键。     

高压 Ti/ 6H- SiC肖特基势垒二极管

在 N型 6 H - Si C外延片上 ,通过热蒸发 ,制作 Ti/ 6 H- Si C肖特基势垒二极管 (SBD) .通过化学气相淀积 ,进行同质外延生长 ,详细测量并分析了肖特基二极管的电学特性 ,该肖特基二极管具有较好的整流特性 .反向击穿电压约为 40 0 V,室温下 ,反向电压 VR=2 0 0 V时 ,反向漏电流 JR 低于 1e- 4 A / cm2 .采用 Ne离子注入形成非晶层 ,作为边缘终端 ,二极管的击穿电压增加到约为 80 0 V.     

3 A/40 V新型肖特基势垒二极管的设计与研制

为提高传统肖特基二极管的击穿电压,减小了器件的漏电流,提高芯片利用率,文中设计研制了适合于裸片封装的新型肖特基势垒二极管(SBD)。利用Silvaco Tcad软件模拟,在器件之间采用PN结隔离,器件周围设计了离子注入形成的保护环,实现了在浓度和厚度分别为7.5×1012 cm-3和5 μm的外延层上,制作出了反向击穿电压45 V和正向导通压降0.45 V的3 A/45 V肖特基二极管,实验和仿真结果基本吻合。此外,还开发了改进SBD结构、提高其电特性的工艺流程。     

一种提高ESD性能的高压SBD器件结构研究

提出了一种新型SBD器件结构,并应用于高压SBD产品的研制。该结构通过在肖特基势垒区的硅表面增加一层表面缓冲掺杂层(Improved Surface Buffer Dope),将高压SBD的击穿点从常规结构的PN结保护环区域转移到平坦的肖特基势垒区,从根本上提高了器件的反向静电放电(ESD)和浪涌冲击能力。经流片验证,采用该结构的10A150VSBD产品和10A200VSBD产品均通过了反向静电放电(HBM模式)8kV的考核,达到目前业界领先水平。该结构工艺实现简单,可以应用于100V以上SBD的批量生产。     

一种隐埋缓冲掺杂层高压SBD器件新结构

提出了一种新型隐埋缓冲掺杂层(IBBD)高压SBD器件,对其工作特性进行了理论分析和模拟仿真验证.与常规高压SBD相比,该IBBD-SBD在衬底上方引入隐埋缓冲掺杂层,将反向击穿点从常规结构的PN结保护环区域转移到肖特基势垒区域,提升了反向静电释放(ESD)能力和抗反向浪涌能力,提高了器件的可靠性.与现有表面缓冲掺杂层...     

Numerical simulation study of current–voltage characteristics of a Schottky diode with inverse doped surface layer

The Poisson’s equation and drift–diffusion equations are used to simulate the current–voltage characteristics of Schottky diode with an inverse doped surface layer. The potential inside the bulk semiconductor near the metal–semiconductor contact is estimated by simultaneously solving these equations, and current as a function of bias through the Schottky diode is calculated for various inverse layer thicknesses and doping concentrations. The Schottky diode parameters are then extracted by fitting of simulated current–voltage data into thermionic emission diffusion equation. The obtained diode parameters are analyzed to study the effect of inverse layer thickness and doping concentration on the Schottky diode parameters and its behavior at low temperatures. It is shown that increase in inverse layer thickness and its doping concentration give rise to Schottky barrier height enhancement and a change in the ideality factor. The temperature dependences of Schottky barrier height and ideality factor are studied. The effect of temperature dependence of carrier mobility on the Schottky diode characteristics is also discussed.     

Optimized design of 4H-SiC floating junction power Schottky barrier diodes

SiC floating junction Schottky barrier diodes were simulated with software MEDICI 4.0 and their device structures were optimized based on forward and reverse electrical characteristics.Compared with the conventional power Schottky barrier diode,the device structure is featured by a highly doped drift region and embedded floating junction region,which can ensure high breakdown voltage while keeping lower specific on-state resistance,solved the contradiction between forward voltage drop and breakdown voltage.The simulation results show that with optimized structure parameter,the breakdown voltage Can reach 4 kV and the specific on-resistance is 8.3 mΩ·cm2.     

Edge current induced failure of semiconductor PN junction during operation in the breakdown region of electrical characteristic

Typical blocking I-V characteristics are shown and analyzed for PN junctions exhibiting a breakdown region above 1000 V from commercial diodes and power MOSFETs. The leakage reverse current of PN junctions from commercial silicon devices available at this time has a flowing component at the semiconductor-passivant material interface around the junction edge.Part of the plotted experimental current-voltage characteristic fits to linear variation and deviation from this variation at higher applied voltage is attributed to non-controlled current flow in the interfacial layer, between the silicon and passivating material from the junction periphery. The thin interfacial layer including atomic layers both from the semiconductor and passivating dielectric material with fixed charges has imperfections resulted from the junction passivation process. For controlled-avalanche PN junctions no deviation from linear voltage dependence of the reverse current is possible until breakdown region practically at right knee appears. For other PN junctions deviation of the reverse current from linear variation results in a breakdown region with round knee and still with visible voltage dependence at current increase. Such soft breakdown region caused by the phenomena in the interfacial layer is exhibited at lower applied reverse voltage than the expected one for breakdown caused by charge carrier avalanche multiplication at the junction. Operation even for short in the soft breakdown region can lead to PN junction failure and for this reason, a maximum working permissible reverse voltage is specified in device data sheet with a value under the breakdown region. Junction failure consists in significantly lower reverse voltage than the initial one or even electrical short-circuit caused by a spot of material degradation in the interfacial layer from the junction periphery. Operation of the controlled-avalanche diode in the breakdown region is possible only for single pulse of short duration and at junction temperature not higher than 175 °C. Above 150-175 °C even for controlled-avalanche diodes deviation from linear variation of the reverse current has been observed and soft breakdown region can appear before the expected avalanche breakdown. Device failure after operation in the breakdown region, caused by spot of material degradation at the junction periphery has occurred in such conditions. For high voltage commercial power MOSFETs operation in the avalanche breakdown region is limited to 150 °C.     

Effect of Inverse Doped Surface Layer in Schottky Barrier Modification: A Numerical Study

Poisson’s equation and the drift–diffusion equations are used to simulate the current–voltage characteristics of a Schottky diode with an inverse doped surface layer. The potential inside the bulk semiconductor near the metal–semiconductor contact is estimated by simultaneously solving these equations, and then current as a function of bias through the Schottky diode is calculated. The Schottky diode parameters are extracted by fitting of simulated data to the thermionic emission diffusion equation. The simulation is carried out for various inverse layer thicknesses and doping concentrations. The obtained diode parameters are analyzed to study the effect of the inverse layer thickness and doping concentration on Schottky diode modification and its behavior at low temperatures. It is shown that an increase in the inverse layer thickness and doping concentration leads to Schottky barrier height enhancement and a change in the ideality factor. The temperature dependences of the Schottky barrier height and ideality factor are also studied.     

MOSFET栅下碰撞电离与击穿研究

研究了场板终端技术对改善 MOSFET栅下电场分布和碰撞电离率的作用 ,结果表明 ,MOSFET在高压应用时 ,漏极靠近表面的 PN结处电场最强 ,决定器件的击穿特性。通过对实验研究与计算机模拟结果的分析 ,表明在不同的栅压下 ,此处场板长度的大小对栅下电场强度有直接的影响 ,合理地控制场板长度能有效地提高器件的击穿电压。     

Hot-electron effects on AlGaAs/InGaAs/GaAs PHEMTs under accelerated DC stresses

The behavior of Schottky gate characteristics before and after hot-electron stress has been a relatively neglected topic. Thus, this paper discussed the effects of hot-electron accelerated stress on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs as they relate to Schottky gate characteristics. It also presents studies of reverse Schottky gate characteristics before and after hot-electron stresses, as related to two major mechanisms: (1) the widening of the depletion region under the gate; and (2) the impact of the carriers trapped under the gate. The former induces a larger Schottky barrier height with a smaller reverse leakage current density than the latter, while the latter induces the opposite. Two hot-electron conditions are used to investigate the impact of the hot-electron stress on the gate leakage current. The gate leakage current decreases after a hot-electron stress, due the effect of hot-electron stress on the Schottky diode characteristics. Moreover, improvement in the noise performance is expected, due to the decrease in the gate leakage current. Both pre- and post-stress noise measurements have been done to demonstrate this.