共查询到19条相似文献,搜索用时 765 毫秒
1.
文章对采用了埋层二氧化硅抗总剂量加固工艺技术的SOI器件栅氧可靠性进行研究,比较了干法氧化和湿法氧化工艺的栅氧击穿电荷,干法氧化的栅氧质量劣于湿法氧化。采用更敏感的12.5nm干法氧化栅氧工艺条件,对比采用抗总剂量辐射加固工艺前后的栅氧可靠性。抗总剂量辐射加固工艺降低了栅氧的击穿电压和击穿时间。最后通过恒压法表征加固工艺的栅氧介质随时间击穿(TDDB)的可靠性,结果显示抗总剂量辐射加固工艺的12.5nm栅氧在常温5.5V工作电压下TDDB寿命远大于10年,满足SOI抗总剂量辐射加固工艺对栅氧可靠性的需求。 相似文献
2.
3.
采用抗辐射0.8μm SOI CMOS加固技术,研制了抗辐射SOI CMOS器件和电路。利用Co60γ射线源对器件和电路的总剂量辐射效应进行了研究。对比抗辐射加固工艺前后器件的Id-Vg曲线以及前栅、背栅阈值随辐射总剂量的变化关系,得到1 Mrad(Si)总剂量辐射下器件前栅阈值电压漂移小于0.15 V。最后对加固和非加固的电路静态电流、动态电流、功能随辐射总剂量的变化情况进行了研究,结果表明抗辐射加固工艺制造的电路抗总剂量辐射性能达到500 krad(Si)。 相似文献
4.
5.
采用硅离子注入工艺对注氧隔离(SIMOX)绝缘体上硅(SOI)材料作出改性,分别在改性材料和标准SIMOXSOI材料上制作部分耗尽环型栅CMOS/SOI器件,并采用10keVX射线对其进行了总剂量辐照试验。实验表明,同样的辐射总剂量条件下,采用改性材料制作的器件与标准SIMOX材料制作的器件相比,阈值电压漂移小得多,亚阈漏电也得到明显改善,说明改性SIMOXSOI材料具有优越的抗总剂量辐射能力。 相似文献
6.
超高总剂量辐射下SOI MOS器件特性研究 总被引:2,自引:0,他引:2
在超高总剂量辐射下,界面电荷的改变对MOS器件的阈值电压影响将越来越显著,甚至会引起NMOS的阈值电压增加,即所谓的“反弹”现象。文章研究的SOI NMOS的阈值电压并没有出现文献中所述的“反弹”,原因可能和具体的工艺有关。另外,通过工艺器件仿真和辐射试验验证,SOI器件在超高总剂量辐射后的漏电不仅仅来自于闽值电压漂移所导致的背栅甚至前栅的漏电流,而是主要来自于前栅的界面态的影响。这样,单纯的对埋层SiO2进行加固来减少总剂量辐射后埋层SiO2中的陷阱正电荷,并不能有效提高SOI MOS器件的抗超高总剂量辐射性能。 相似文献
7.
8.
研究了射线辐照对130 nm部分耗尽(Partially Depleted,PD)绝缘体上硅(Silicon on Insulator,SOI)工艺MOS器件栅氧经时击穿(Time-Dependent Dielectric Breakdown,TDDB)寿命的影响。通过测试和对比辐照前后NMOS和PMOS器件的转移特性曲线、阈值电压、关态泄漏电流以及TDDB时间等电参数,分析了射线辐照对PD-SOI MOS器件TDDB可靠性的影响。结果表明:由于射线辐照在栅极氧化层中产生了带正电的氧化物陷阱电荷,影响了器件内部势垒的分布,降低了电子跃迁的势垒高度,导致了电子遂穿的正反馈作用增强,从而缩短了器件栅氧化层经时击穿时间,最终造成器件栅极氧化层的可靠性下降。 相似文献
9.
10.
11.
This study investigates the effects of oxide traps induced by SOI of various thicknesses (TSOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner TSOI devices have a smaller net remaining stress in gate oxide film than thicker TSOI devices, and thus possess a smaller bulk oxide trap (NBOT) and reveal a superior gate oxide reliability. On the other hand, the thicker TSOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker TSOI device has a higher bulk oxide trap (NBOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker TSOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability. 相似文献
12.
静态电流测试是一种高灵敏度、低成本的集成电路失效分析技术,在集成电路故障检测、可靠性测试及筛选中的应用日益普遍。针对某绝缘体上硅专用集成电路在老炼和热冲击实验后出现的静态电流测试失效现象,结合样品伏安特性、光发射显微镜和扫描电子显微镜等电学和物理失效分析手段,确定了栅氧化层中物理缺陷的存在、位置及类型;结合栅氧化层经时介质击穿原理分析,揭示了样品的主要失效机理,并分析了经时介质击穿失效的根源,为改进工艺、提高电路可靠性提供了依据。 相似文献
13.
Ushiki T. Mo-Chiun Yu Hirano Y. Shimada H. Morita M. Ohmi T. 《Electron Devices, IEEE Transactions on》1997,44(9):1467-1472
A reliable tantalum (Ta)-gate device technology, which can drastically reduce the number of process steps, has been developed. Ta-gate fully-depleted-silicon-on-insulator (FDSOI) MOSFETs with 0.15-μm gate length by low-temperature processing below 500°C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta-gate MOSFETs in the deep-submicrometer regime is provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. In the guideline, the recrystallization of the source/drain region gives inferior limits of the SOI thickness and the process temperature. Thermal reaction between Ta and SiO2 films sets a superior limit of the process temperature, and a short-channel effect sets a superior limit of the SOI thickness 相似文献
14.
Lin C.-L. Chen Y.-T. Huang F.-S. Yeh W.-K. Lin C.-T. 《Electron Device Letters, IEEE》2010,31(2):165-167
15.
Sung Bae Park Young Wug Kim Young Gun Ko Kwang Il Kim Il Kwon Kim Hee-Sung Kang Jin Oh Yu Kwang Pyuk Suh 《Solid-State Circuits, IEEE Journal of》1999,34(11):1436-1445
A 0.25-μm, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm2 silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test 相似文献
16.
17.
Noguchi M. Numata T. Mitani Y. Shino T. Kawanaka S. Oowaki Y. Toriumi A. 《Electron Device Letters, IEEE》2001,22(1):32-34
The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide 相似文献
18.
Jong-Wook Lee Hyung-Ki Kim Ji-Woon Yang Won-Chang Lee Jeong-Hee Oh Min-Rok Oh Yo-Hwan Koh 《Electron Device Letters, IEEE》1999,20(4):176-178
The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10% 相似文献