复合型微通道热沉设计与制作技术研究

从大功率半导体激光器可靠性封装和应用考虑,利用商用有限元软件Abaqus与CFdesign对微通道热沉材料、结构进行优化设计,结合相应的制造工艺流程制备实用化复合型微通道热沉。微通道热沉尺寸为27 mm×10.8 mm×1.5 mm,并利用大功率半导体激光阵列器件对所制备热沉进行散热能力、封装产生的"微笑效应"进行了测试,复合微通道热沉热阻约0.3 K/W,"微笑"值远小于无氧铜微通道封装线阵列,可以控制在1μm以下。复合型微通道热沉能满足半导体激光阵列器件高功率集成输出的散热需求与硬焊料封装的可靠性要求。     

共晶焊料焊接的孔隙率研究

大功率或高功率密度的高可靠集成电路等通常采用合金焊料焊接芯片,以降低封装热阻和提高芯片焊接的可靠性。合金焊料焊接方式主要有真空烧结、保护气氛下静压烧结、共晶摩擦焊等。不同焊接工艺有其不同的适应性和焊接可靠性。文章以高可靠封装常用金基焊料的共晶焊接为例,探讨在相同封装结构、不同共晶焊接工艺下焊接层孔隙率,以及相同工艺设备、工艺条件下随芯片尺寸增大孔隙率的变化趋势。研究结果表明:金-硅共晶摩擦焊工艺的孔隙率低于金-锡真空烧结工艺和金-锡保护气氛静压烧结;同一焊接工艺,随着芯片尺寸变大,其孔隙率变化不显著,但单个空洞的尺寸有明显增大趋势。     

大功率LED低热阻封装技术进展

散热是大功率LED封装的关键技术之一,散热不良将严重影响LED器件的出光效率、亮度和可靠性。影响LED器件散热的因素很多,包括芯片结构、封装材料(热界面材料和散热基板)、封装结构与工艺等。文章具体分析了影响大功率LED热阻的各个因素,指出LED散热是一个系统概念,需要综合考虑各个环节的热阻,单纯降低某一热阻无法有效解决LED的散热难题。文中还对国内外降低LED热阻的最新技术进行了介绍。     

烧结温度对AuSn焊料薄膜及封装激光器性能的影响

采用不同温度对Au80Sn20共晶合金焊料进行烧结实验,研究了AuSn焊料薄膜在烧结后的形貌、物相组成以及对封装激光器的性能影响等.焊料在烧结后形成ξ相Au5Sn和δ相AuSn两种金属间化合物,随着烧结温度的上升,两相晶粒均明显长大,而ξ相Au5Sn趋向于形成枝晶.较低温度下烧结的焊料表面粗糙度较高,不利于激光器管芯的贴装.高温过烧焊料薄膜的导电导热性能有少许提升,对封装激光器管芯的功率没有明显影响,但焊料薄膜中残余应力较高,使激射波长有所蓝移.该结果将为AuSn焊料的烧结参数优化和硬焊料封装激光器的性能分析提供参考和指导.     

压接式GCT封装的热特性分析

电力半导体器件的散热性能和热可靠性与其封装结构密切相关,选择合适的封装结构对改善器件的散热性能和提高热可靠性非常重要。文中根据压接式GCT器件封装结构特点,采用ANSYS软件利用有限元法分析了单芯片封装和多芯片封装结构的温度及热机械应力分布,并与常规的焊接式封装进行了对比。结果表明,压接式封装结构的散热效果比焊接式封装结构稍差,但其芯片上产生的热机械应力明显减小。多芯片封装采用常规的风冷散热器时芯片温度已经超过了器件的安全工作温度(125℃),应该采用热管散热器才能保证器件可靠地工作。     

连续波80W大功率SiC MESFET

在高纯半绝缘(HPSI)衬底上外延生长了SiC材料,自主开发了SiC MESFET器件制作工艺,实现了单胞栅宽27 mm芯片的制作。优化了芯片装配形式,通过在管壳内外引入匹配网络提升了芯片输入阻抗及输出阻抗。利用管壳外电路匹配技术,采用管壳内匹配及外电路匹配相结合的方法对器件阻抗进行了进一步提升。优化了管壳材料结构,采用无氧铜材料提高了管壳散热能力。采用水冷工作的方式解决了大功率器件散热问题,降低了器件结温,可靠性得到提高。采用多胞芯片匹配合成技术,实现四胞4×27 mm芯片大功率合成。四胞芯片封装器件在连续波工作频率为2 GHz、Vds为37.5 V时连续波输出功率达80.2 W(49.05 dBm),增益为7.0 dB,效率为32.5%。     

高功率二极管激光器Au80Sn20焊料焊接实验研究

半导体激光器封装工艺过程对于激光器的输出特性、寿命等性能有重要影响,其中焊料的选择和焊接工艺是最关键的因素。本文采用磁控溅射的方法,在 WCu 热沉上制备了Au80Sn20合金焊料,取代了传统的In焊料,并对焊接工艺进行了改进。国外沉积的和我们制备的Au80Sn20合金焊料焊接DL芯片后的性能参数很接近。充分说明双靶分层溅射镀膜可以实现二极管激光器的封装要求,从而为优化半导体激光器制备工艺和提高半导体激光器的性能奠定基础。     

混合烧结高散热导电胶的封装应用及性能

为满足中大尺寸背面裸硅芯片的封装应用及其高散热需求,开发了一种新型混合烧结高散热导电胶,该新型导电胶以有机二元酸表面活化的银粉颗粒、丙烯酸树脂和其他有机添加剂为原料混合制备而成.采用新型导电胶将6 mm×6 mm裸硅芯片粘接到方形扁平无引脚封装键合(QFNWB)产品上,并进行了导电胶黏度测量、X射线无损检测、导电胶和芯片粘接的破坏性推力测试、导热系数测试和可靠性试验.研究结果表明,该导电胶触变指数为7.2,烘烤后无明显气孔产生,6 mm×6 mm裸硅芯片粘接的破坏性推力为343 N,导热系数高达15 W/(m·K).与常规导电胶相比,其导热性能优异,且解决了烧结银导电胶无法应用于中大尺寸背面裸硅芯片的问题,满足产品的高散热和高可靠性要求.     

气密性陶瓷封装PIND失效分析及解决方案

气密性陶瓷封装腔体内的自由粒子会严重影响到器件的可靠性。减少封装腔体内自由粒子数量,提高PIND合格率是气密性封装的主要技术之一。文章就陶瓷外壳封装集成电路PIND失效进行了分析,指出其主要原因,如外壳内部有瓷颗粒、芯片边缘未脱落的硅碴(屑)、芯片边沿的粘接材料卷起、脱落的粘接材料碎片、键合丝(或尾丝)、悬伸的合金焊料、封帽飞溅的合金焊料、平行缝焊打火飞溅的焊屑等,并提出了在封装工艺过程中如何对可能产生自由粒子的因素采取有效预防措施。最终使电路的粒子碰撞噪声检测合格品率达到98%以上,达到实际应用要求。     

贴片焊层厚度对功率器件热可靠性影响的研究

贴片工艺是用粘接剂将芯片贴装到金属引线框架(一般是由铜制成)上的过程.富铅的Pb/Sn/Ag软焊料在功率器件封装贴片工艺中作为粘接剂应用十分广泛.从功率器件整体来看,贴片焊层毫无疑问是影响器件可靠性最重要的因素之一,其不仅具有良好的导电导热性能,而且该焊层能够吸收由于芯片和引线框架之间的热失配而产生的应力应变,保护芯片免于受到机械应力的损伤.基于Darveaux的热疲劳寿命分析模型,利用功率循环加速实验以及有限元方法具体分析了贴片焊层厚度BLT对于功率器件热可靠性的影响.并通过实验与仿真的结果,提出提高功率器件热可靠性的设计原则.     

Fluxless Bonding of Large Silicon Chips to Ceramic Packages Using Electroplated Eutectic Au/Sn/Au Structures

A fluxless process of bonding large silicon chips to ceramic packages has been developed using a Au-Sn eutectic solder. The solder was initially electroplated in the form of a Au/Sn/Au multilayer structure on a ceramic package and reflowed at 430°C for 10 min to achieve a uniform eutectic 80Au-20Sn composition. A 9 mm × 9 mm silicon chip deposited with Cr/Au dual layers was then bonded to the ceramic package at 320°C for 3 min. The reflow and bonding processes were performed in a 50-mTorr vacuum to suppress oxidation. Therefore, no flux was used. Even without any flux, high-quality joints were produced. Microstructure and composition of the joints were studied using scanning electron microscopy with energy-dispersive x-ray spectro- scopy. Scanning acoustic microscopy was used to verify the joint quality over the entire bonding area. To employ the x-ray diffraction method, samples were made by reflowing the Au/Sn/Au structure plated on a package. This was followed by a bonding process, without a Si chip, so that x-rays could scan the solder surface. Joints exhibited a typical eutectic structure and consisted of (Au,Ni)Sn and (Au,Ni)₅Sn phases. This novel fluxless bonding method can be applied to packaging of a variety of devices on ceramic packages. Its fluxless nature is particularly valuable for packaging devices that cannot be exposed to flux such as sensors, optical devices, medical devices, and laser diodes.     

Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

倒装焊器件封装结构设计

倒装焊是今后高集成度半导体的主要发展方向之一。倒装焊器件封装结构主要由外壳、芯片、引脚(焊球、焊柱、针)、盖板(气密性封装)或散热片(非气密性封装)等组成。文章分别介绍外壳材料、倒装焊区、频率、气密性、功率等方面对倒装焊封装结构的影响。低温共烧陶瓷(LTCC)适合于高频、大面积的倒装焊芯片。大功率倒装焊散热结构主要跟功率、导热界面材料、散热材料及气密性等有关系。倒装焊器件气密性封装主要有平行缝焊或低温合金熔封工艺。     

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

Effect of solder creep on the reliability of large area die attachment

High temperature solders have been widely used for power device die attachment. One typical solder is Pb92.5In5Ag2.5, which is a ternary eutectic alloy with a eutectic temperature of 310°C. Such a Pb-based solder has a low Young's modulus, a low yield strength, and a high strain prior to failure. So it can be used to attach large size silicon die to mismatched substrates. In this paper, stresses and strains have been studied on a large size power MOSFET attachment using the Pb92.5In5Ag2.5 solders. A commercial finite element analysis software is employed as the simulation tool. Three types of substrates, pure copper, copper–tungsten composite, and pure molybdenum are used in the study, where molybdenum has the closest coefficient of thermal expansion to silicon. In addition to the plastic deformation simulation of the solder, a creep model of the solder was incorporated due to the low melting temperature of the solder alloy. Firstly, stresses and strains are calculated during the cooling cycle after attachment. It is found that the creep strain is the dominant plastic strain at low cooling rate (10°C/min). Also, the maximum Von Mises stress in the Si chip is decreased from 174 to 62.7 MPa after adding creep strain. As expected, the maximum creep strain happens to the die-to-copper substrate attach. Simulation on temperature cycling is done from −55°C to +150°C. The peak Von Mises stress occurs at the low temperature extreme and holds steadily during the soaking period, indicating insignificant contribution from creep. The Von Mises stress at the high temperature extreme is much lower and decreases with holding time. Significant plastic deformation of the solder layer is observed in cooling cycles. For silicon to copper substrate attach, its plastic deformation increases with each cycle. For all three substrates used, considerable solder creep is observed at heating cycles. The creep strain is much larger than the rate-independent plastic strain in the solder alloy for all three types of substrates. It is concluded that solder creep is the dominant factor affecting long term reliability of power semiconductor die attachment.     

电子封装热管理的热电冷却技术研究进展

电子封装器件中芯片的散热问题一直是制约其发展的瓶颈。综述了芯片的产热特征、散热需求与散热方式。对热电冷却(TEC)技术在芯片散热系统上的应用进行分析,指出了其不足之处与特有的优势。对热电冷却技术在芯片热管理方面应用研究的现状与进展进行了总结评述。     

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged.