Miniaturized reverse modulation loop of a CQPSK 120 Mbit/s modemfor spacecraft applications

The design and performance of a miniaturized reverse modulation loop (RML) for a 120 Mbit/s coherent quadrature phase shift keying (CQPSK) modem for onboard satellite applications are presented. Analysis of time delays within the RML circuit indicates that any differential time-delay errors can adversely affect the associated BER and should be minimized. The RML circuit, consisting of a modulator, demodulator, and comparator circuit, has been fabricated using quasi-monolithic techniques with dimensions of 1.65×4 cm. The relative phase for all four states of the modulator is in close agreement with design values of 90°±1° over a 200 MHz bandwidth at 3.95 GHz. The demodulator and comparator circuits of the RML have successfully recovered a 120 Mbit/s bit stream. The RML circuit is capable of recovering higher bit rates because of relatively uniform amplitude and phase performance over the 3.7- to 4.2 GHz communications satellite band     

Gigabit QPSK modulator

We describe a QPSK (quaternary phase shift keyed) modulator operating at gigabit data transmission rates at a carrier frequency of 13 GHz. The modulator circuit can also be operated as a QPSK demodulator. A modulator-de-modulator pair operating in tandem showed clean eye diagrams of the recovered data trains on each port up to l.5 Gbit/s with corresponding error rates of less than 10?11. The circuit can be readily scaled to higher frequencies with a proportional increase in the information rate.     

35–65-GHz CMOS Broadband Modulator and Demodulator With Sub-Harmonic Pumping for MMW Wireless Gigabit Applications

Sub-harmonic modulator and demodulator are presented in this paper using 0.13-mum standard CMOS technology for millimeter-wave (MMW) wireless gigabit direct-conversion systems. To overcome the main problem of local oscillator (LO) leakage in direct-conversion systems, the sub-harmonically pumped scheme is selected in this mixer design. An embedded four-way quadrature divider is utilized in the sub-harmonic Gilbert-cell design to generate quadrature-phases LO signals at MMW frequency. For broadband applications, a broadband matching design formula is provided in this paper to extend the operational frequency range from 35 to 65 GHz. To improve the flatness of conversion loss at high frequency, high-impedance compensation lines are incorporated between the transconductance stage and LO switching quad of the Gilbert-cell mixer to compensate the parasitic capacitance. The sub-harmonic modulator and demodulator exhibit 6 plusmn1.5 dB and 7.5 plusmn1.5 dB measured conversion loss, respectively, from 35 to 65 GHz. For MMW wireless gigabit applications, the gigabit modulation signal test is successfully performed through the direct-conversion system in this paper. To our knowledge, this is the first demonstration of the MMW CMOS sub-harmonic modulator and demodulator that feature broadband and gigabit applications.     

Monolithic demodulator for high sensitivity 2.5 Gbit/s CPFSKreceiver

A completely monolithic quadrature demodulator for an optical heterodyne CPFSK receiver is reported for the first time. The demodulator is realised as a GaAs MMIC and operates up to 2.5 Gbit/s at an intermediate frequency of 9.8 GHz, yielding a receiver sensitivity of -42.5 dBm     

GaAs MMIC demodulator using a distributed mixing principle forhigh-sensitivity 5 Gbit/s CPFSK receiver

A distributed GaAs MMIC mixer is designed to be employed in an integrated demodulator for a coherent optical CPFSK receiver with an IF bandwidth of 7-14 GHz and a baseband bandwidth of 4 GHz. At 5 Gbit/s a receiver sensitivity of -39.0 dBm is obtained using the demodulator     

A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication

The feasibility of a 40 Gb/s subcarrier modulated optical transmission system using low-cost optoelectronic components and CMOS IC technology is presented. The optical channel impairments are studied. A complete DSP framework is developed to cancel out the optical channel impairments as well as analog circuit imperfections. To validate that the 40 Gb/s system can be implemented in CMOS, an integrated QAM-16 transceiver with a carrier frequency of 13.32 GHz was designed and fabricated in a 0.14$muhbox m$, 1.5 V CMOS technology. The test chip occupies 3.6$hbox mm^2$of area and consumes 340 mW of power. Measurement results for a transmission link consisting of the CMOS QAM-16 modulator/demodulator, a directly modulated laser (DML), a 30 km single mode fiber and a p-i-n photo-detector are reported.     

Switched-capacitor FSK modulator and demodulator in CMOS technology

A switched-capacitor FSK modulator/demodulator built in silicon-gate CMOS technology is described. The modulator is based on a programmable harmonic oscillator using two stray-insensitive integrators. The centerpiece of the FSK demodulator is a switched-capacitor voltage-controlled oscillator. A simple post-detection processor restores the digital data. Both circuits have been designed for the 600-baud modem channel with 1500 Hz center frequency and /spl plusmn/200 Hz frequency shifts, but the demodulator operates in the 1200-baud channel as well. Due to dynamic biasing the operational amplifiers feature high slew rate, high voltage gain, and low power for capacitive loads.     

Surface transverse wave based FM modulator/demodulator

An FM modulator/demodulator system employing three identical surface transverse wave (STW) resonators is described. It operates at a centre frequency of 1012 MHz and can transmit data at over 100 kbit/s. This low cost system has a low noise and can detect FM signals with a deviation of less than 0.1 ppm.<>     

高速无线数据传输中的补码键控扩频调制

补码键控扩频调制在克服多径效应、抗频率选择性衰落及抗窄带干扰方面有着优异的性能.IEEE802.11b标准规定采用补码键控技术以达到11Mbps,5.5Mbps的数据传输速率.介绍了该技术中采用的码字及其结构,并详细地给出了其调制与解调的具体实现.     

Ultrahigh-speed driverless MQW intensity modulator, and 20 Gbit/s, 100 km transmission experiments

An InGaArInAlAs MQW modulator with the low voltage of 1.5 V for 10 dB extinction ratio and 16 GHz bandwidth has been developed. This ultrahigh-speed modulator enables the modulator driver to be eliminated from the transmitter. 100 km transmission experiments have been carried out using either a 1 V peak to peak output monolithic-IC-driven modulator at 15 Gbit/s or a 2 V peak to peak output multiplexer-driven modulator at 20 Gbit/s. This is the first report on multigigabit operation of MQW modulators to the authors' knowledge.<>     

基于FPGA的RFID调制解调器设计

介绍了基于UHF Class 1 Generation 2协议标准的RFID系统的调制、解调算法.在FPGA上实现了调制器和解调器,调制器可根据用户需要选择DSB-ASK、SSB-ASK或PR-ASK调制方式,解调器能同时解调2ASK和BPSK信号.使用Quartus Ⅱ与MATLAB联合仿真,结果表明设计的RFID调制器和解调器是正确的.     

基于相位调制器倍频技术产生56GHz毫米波的光载无线通信系统

提出并实验研究了一种基于光相位调制器(PM)倍频技术产生56GHz毫米波的光载无线通信(RoF)系统。在中心站,通过28GHz射频(RF)信号驱动PM产生了56GHz光毫米波,并将下行的2.8Gb/s开关键控(OOK)信号调制到该光载波上,然后经过20km标准单模光纤(SSMF)传输至基站,最后由天线进行发射。用户终端接收后,采用相干解调恢复出基带信号。实验结果表明,56GHz光载毫米波信号经SSMF传输20km后其功率代价小于1dB,通过无线方式传输1.1m后其功率代价小于2.5dB。     

A 2.7-V GSM RF transceiver IC

A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for receivers. Power-control functions are provided for independent transmit and receive operation. The IC is implemented by using bipolar technology with f_T=15 GHz, r'_bb=150 Ω, and 0.6-μm features     

一种基于相位调制器的40 GHz OFDM-ROF系统实验研究

实验研究了一种基于相位调制器(PM)并级联强度调制器(IM)实现40 GHz毫米波传输正交频分复用(OFDM)信号的光纤无线通信(ROF)系统。在中心站,采用20 GHz的射频(RF)信号驱动PM,调节驱动信号的强度,使输出的信号经光纤布拉格光栅(FBG)滤除中心载波后再送入IM。2.5 Gbit/s的OFDM信号直接调制在光毫米波上,经过50 km标准的单模光纤(SSMF)传输到基站。在基站,光调制信号经光电转换器(PD)转换成电调制信号,再与RF信号混频,恢复出基带OFDM信号。实验结果表明,在无色散补偿、误码率(BER)为10-3的条件下,下行链路中2.5 Gbit/s的OFDM信号经光纤传输50 km后,其功率代价小于1 dB,而且信号的星座图依然较好。     

A VLSI architecture for a high-speed all-digital quadraturemodulator and demodulator for digital radio applications

An all-digital architecture is presented for implementing the front-end signal-processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25-μm process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR (finite-impulse response) square-root Nyquist matched filters, and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256×256 points. Thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using formats such as M-ary PSK and QAM     

Modulator driver and photoreceiver for 20 Gb/s optic-fiber links

Two integrated circuits, a modulator driver and a photoreceiver integrating a metal-semiconductor-metal (MSM) photodetector, a differential transimpedance amplifier and two limiting amplifier stages for high-speed optical-fiber links are presented. The IC's were manufactured in a 0.2 μm gate-length AlGaAs-GaAs high-electron mobility transistor (HEMT) technology with a f_T of 60 GHz. The modulator driver IC operates up to 25 Gb/s with an output voltage swing of 3.3 V_p-p at each output. The 1.3-1.55 μm wavelength monolithically integrated photoreceiver optoelectronic integrated circuit (OEIC) has a bandwidth of 17 GHz with a high transimpedance gain of 12 kΩ. Eye diagrams are demonstrated at 20 Gb/s with an output voltage of 1 V_p.p     

Full polarization insensitivity of a 20 Gb/s strained-MQWelectroabsorption modulator

We report on a MQW electroabsorption modulator with tensile-strained wells. The device transmission is shown to be fully polarization insensitive, i.e. both in amplitude and phase. The modulation efficiency is over 20 GHz/V (bandwidth higher than 20 GHz and 1 V drive voltage) which is the highest figure of merit reported for any kind of polarization insensitive modulator. Full polarization independence is further demonstrated by 2.5 Gb/s transmission at 1.55 μm over 475 km of standard fiber without penalty at 10^-9 BER whatever the polarization     

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP₃) is -3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.     

ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network

This paper presents an architecture as well as circuit implementation of a ZigBee modulator/demodulator in the transceiver for personal area network, which is compliant with the physical layer of IEEE standard 802.15.4. A test prototype has been designed and fabricated using 0.18-mum single-poly six-metal CMOS process with core area of 0.16 mm² . The measurement results show that packet error rate (PER) is less than 1% given SNR = 5 dB. The total power consumption is merely 251 muW at a 2.4-MHz system clock.     

GMSK Demodulator Implementation for ESA Deep-Space Missions

This paper discusses a new implementation of a Gaussian minimum-shift keying (GMSK) modulator and demodulator on the European Space Agency (ESA)'s common deep-space receiver-the Intermediate Frequency Modem System (IFMS), which is a software radio based platform. The GMSK demodulator is needed for ESA's deep-space and near-Earth missions, starting with the Herschel-Planck satellites in 2008. The implementation requirements and hardware restrictions from the IFMS lead to the need for a significant simplification versus the optimum demodulation approach. In part, this can be achieved by using a demodulator based on the Laurent decomposition, yet further simplifications and changes to obtain a feasible implementation were necessary. The presented GMSK demodulator was directly implemented on the existing IFMS receiver without requiring any hardware changes. Measurements with the demodulator showed only a marginal technical degradation in the order of 0.1-0.3 dB for the chosen approach. Furthermore, for testing purposes, a GMSK modulator was implemented on the same platform.