Simple weight-integrating A/D converters with high noise rejection

It is shown that the use of simple weight-integrating functions (stepwise or triangle) in integrating A/D converters ensures a high level of noise rejection (NMRR-up to 80 dB if the actual period of power line-related noise differs from its nominal value by less than ±1%). This result can be improved (with NMRR up to 90 dB and more) if the time of weight integration is synchronized with the actual or predicted noise period. Theoretical and experimental data are considered and discussed     

Code probability distributions of A/D converters with random inputnoise

The specific architecture of an A/D converter influences the code probability distributions that result from random input noise. In particular, the output codes of successive approximation A/D converters have a spiked distribution, and its variance is half that of the corresponding input noise. In addition, the distribution has a small bias. These and other related results are derived, and are qualitatively supported by measurement data on a real 16-bit A/D converter     

Speed-limiting factors in flash-type Josephson A/D converters

The authors discuss the causes of speed limitations in various A/D (analog/digital) converter designs. The upper limit on bandwidth is extracted with the help of Josephson SPICE simulations. In the Josephson A/D converter circuits discussed, the dynamic properties of the SQUIDs (superconducting quantum interference devices) determine the aperture time and dictate the bandwidth. Designs for 4-bit A/D converters that show potential for bandwidths on the order of 10 GHz are described. Particular attention is given to the bit-parallel A/D converter with self-gating AND comparator and bit-parallel A/D converters with CLAM (current latching analog microcomparator) and variable-pulse peak comparators     

Digital calibration for monotonic pipelined A/D converters

The original digital calibration approach for 1 b/stage and 1.5 b/stage pipeline analog-digital converters produces missing or nonmonotonic digital codes with the device and circuit impairments typical of modern deep submicrometer CMOS technologies. Two digital calibration algorithms are introduced to improve pipeline performance when using low-voltage low-gain nonlinear operational amplifiers and high random dc offset voltage comparators. The first technique computes calibration coefficients for each stage at actual transition points of the residue characteristic to assure converter monotonicity in the presence of random comparator offset voltages. The second augments a conventional pipelined architecture with an input-dependent level-shifting stage and additional digital calibration circuitry to achieve high differential and integral linearity with low-gain nonlinear operational amplifiers.     

Compact FPGA-based beamformer using oversampled 1-bit A/D converters

A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.     

INL reconstruction of A/D converters via parametric spectral estimation

The work presented in this paper builds on previous research done by the authors in detailing a novel procedure for obtaining a very fast measurement of the integral nonlinearity of an analog-to-digital converter (ADC). The core of the method is the parametric spectral estimation of the ADC output; the static characteristic is subsequently reconstructed as a sum of Chebyshev polynomials, in accordance with a previously developed procedure. The method allows one to test an ADC with sinusoids of any reasonable amplitude (even a slight overdrive is allowed), frequency (no synchronization is needed), and phase (which is digitally compensated). This approach is less accurate than the histogram test but incomparably faster (about 8000 samples are sufficient regardless of the ADC resolution).     

Analysis of distortion in A/D converters by time-domain andcode-density techniques

Two new methods for measuring the total harmonic distortion of an A/D converter are described. One is based on time-domain analysis, the other on modified code density analysis. Experiments show that these methods give results comparable to the ones provided by FFT analysis. It is then shown, by both experiments on a flash converter and computer simulations, that the conventional code density analysis does not provide accurate signal-to-noise-plus-distortion ratio (SNDR) estimates at the highest frequencies, while the proposed methods do     

Analysis of mismatch effects among A/D converters in atime-interleaved waveform digitizer

High-speed A/D conversion can be achieved by employing a parallel array of M A/D converters interleaved in time, each working at 1/Mth of the sampling rate. Theoretically, the resolution of the structure is given by the resolution of the A/D converters in the array (subconverters). In practice, however, mismatches among the subconverters lead to a decrease in the resolution. The effect of such mismatches is analyzed in terms of a signal-to-noise ratio defined as the ratio between the energy of the input analog signal and the energy of the error signal due exclusively to these mismatches. The analysis shows that the distortion is comparable to that generated by nonuniform sample timing in the analog demultiplexer when converting a single high-speed signal into several low-speed sampled-and-held signals. The results of the analysis can be used to specify the degree of precision to be achieved in an actual monolithic implementation     

An improved code density test for the dynamic characterization offlash A/D converters

An improved code density test for flash A/D converters is proposed, revealing some dynamic phenomena (e.g., missing codes) hidden by the conventional approach. Formulas are reported for obtaining, from code density, effective noise estimates fully consistent with those provided by waveform analysis. Finally, it is shown that the variance of noise estimates obtained by time-domain analysis may be unacceptably large if the observation window is not properly chosen     

Measurement of timing jitter contributions in a dynamic test setupfor A/D converters

The article provides a new method which permits one to separate and to obtain an accurate estimation of timing jitter contributions appearing in an analog-to-digital (A/D) converter dynamic common test setup. The results are obtained using coherent sampling configuration and are independent of quantization and nonlinearities of the converter     

一种适用于流水线ADC的数字校准算法的硬件实现

研究了一种适用于开关电容级电路结构的流水线ADC的数字后台校准算法并提出了其硬件实现方法.此算法适用于每级1.5bit和多bit的子级转换电路,实时地监控关键子级电路转换函数的特性,并从数字输出中提取校准信息,不中断正常的转换过程.文中提出的硬件实现方法通过有限状态机实现该算法,实现了各模块高效的协同工作.仿真证明用该硬件实现方法设计的校准处理系统能够有效校准电容失配和运放有限增益误差.     

A piezoelectric screw dislocation interacting with a nonuniformly coated circular inclusion

This paper investigated the interaction of a piezoelectric screw dislocation with a nonuniformly coated circular inclusion in an unbounded piezoelectric matrix subjected to remote antiplane shear and electric fields. In addition to having a discontinuous displacement and a discontinuous electric potential across the slip plane, the dislocation is subjected to a line force and a line charge at the core. The alternating technique in conjunction with the method of analytical continuation is applied to derive the general solutions in an explicit series form. This approach has a clear advantage in deriving the solution to the heterogeneous problem in terms of the solution for the corresponding homogeneous problem. The presented series solutions have rapid convergence which is guaranteed numerically. The image force acting on the piezoelectric screw dislocation is calculated by using the generalized Peach–Koehler formula. The numerical results show that the varying thickness of the interphase layer will exert a significant influence on the shear stress and electric field within the circular inclusion, and on the direction and magnitude of the image force. This solution can be used as Green’s function for the analysis of the corresponding piezoelectric matrix cracking problem.     

Precision average-sensing AC/DC converters

Various configurations of average-sensing AC/DC converters for precision AC voltage measurements are described. Due to the unique electrical configurations in which the influence of the inaccuracy of ratio resistors is suppressed, these converters have high accuracy (better than 0.01%) and resolution (0.0001%) at medium frequencies. Their frequency range is from 10 Hz to 1 MHz, with a settling time less than 1 s     

A flash Josephson A/D converter constructed with one-junctionSQUIDs

A novel approach to the construction of a flash-type Josephson A/D (analog/digital) converter is presented. Simulations show that one-junction SQUID (superconducting quantum interference device) comparators can have a greater than fivefold advantage in bandwidth over the two- or three-junction SQUIDs in an A/D circuit. Assuming a Nb junction technology, the simulations show that a 6-bit A/D converter using one-junction SQUID comparators could have a sampling rate of ~20 GHz with ~5 bits of resolution for a 5-GHz input signal. Detailed analysis and simulations of an A/D converter constructed with one-junction SQUIDs are presented. Further improvement can be made by using a coding algorithm which requires 2N-1 comparators, instead of N, for an N-bit A/D converter