热载流子应力下超薄栅pMOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了4nm pMOSFET的热载流子应力下氧化层陷阱电荷的产生行为.首先,对于不同沟道长度下的热载流子退化,通过直接的实验证据,发现空穴陷阱俘获特性与应力时间呈对数关系.然后对不同应力电压、不同沟道长度下氧化层陷阱电荷(包括空穴和电子陷阱俘获)的产生做了进一步的分析.发现对于pMOSFET的热载流子退化,氧化层陷阱电荷产生分两步过程:在较短的应力初期,电子陷阱俘获是主要机制;而随着应力时间增加,空穴陷阱俘获作用逐渐显著,最后主导了氧化层陷阱电荷的产生.     

热载流子应力下超薄栅p MOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了 4nmpMOSFET的热载流子应力下氧化层陷阱电荷的产生行为 .首先 ,对于不同沟道长度下的热载流子退化 ,通过直接的实验证据 ,发现空穴陷阱俘获特性与应力时间呈对数关系 .然后对不同应力电压、不同沟道长度下氧化层陷阱电荷 (包括空穴和电子陷阱俘获 )的产生做了进一步的分析 .发现对于 pMOSFET的热载流子退化 ,氧化层陷阱电荷产生分两步过程 :在较短的应力初期 ,电子陷阱俘获是主要机制 ;而随着应力时间增加 ,空穴陷阱俘获作用逐渐显著 ,最后主导了氧化层陷阱电荷的产生.     

衬底热空穴注入下的薄栅氧化层击穿特性

利用衬底热空穴 (SHH)注入技术 ,分别定量研究了热电子和空穴注入对薄栅氧化层击穿的影响 ,讨论了不同应力条件下的阈值电压变化 .阈值电压的漂移表明是正电荷陷入氧化层中 ,而热电子的存在是氧化层击穿的必要条件 .把阳极空穴注入模型和电子陷阱产生模型统一起来 ,提出了薄栅氧化层的击穿是与电子导致的空穴陷阱相关的 .研究结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡 .认为栅氧化层的击穿是一个两步过程 .第一步是注入的热电子打断 Si— O键 ,产生悬挂键充当空穴陷阱中心 ,第二步是空穴被陷阱俘获 ,在氧化层中产生导电通路     

衬底热空穴注入下的薄栅氧化层击穿特性

利用衬底热空穴(SHH)注入技术,分别定量研究了热电子和空穴注入对薄栅氧化层击穿的影响,讨论了不同应力条件下的阈值电压变化.阈值电压的漂移表明是正电荷陷入氧化层中,而热电子的存在是氧化层击穿的必要条件.把阳极空穴注入模型和电子陷阱产生模型统一起来,提出了薄栅氧化层的击穿是与电子导致的空穴陷阱相关的.研究结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡.认为栅氧化层的击穿是一个两步过程.第一步是注入的热电子打断Si一O键,产生悬挂键充当空穴陷阱中心,第二步是空穴被陷阱俘获,在氧化层中产生导电通路,薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

关于薄SiO_2的高场弛豫电导与击穿机制的研究

薄SiO_2的早期高场弛豫电导与原生电子陷阱的俘获及新生正电荷的产生密切相关;中、后期的电导弛豫与新生电子陷阱的产生-俘获过程相关,新生电子陷阱遵从单分子产生规律.一个“新生电子陷阱-新生SiO_2/Si_2O,界面陷阱相关击穿”模型,用以解释薄SiO_2的后期弛豫电导突变失控和不可逆转的失效——脉冲热击穿.     

MOSFET不同厚度薄栅老化中 SILC的机制

通过对栅电流和栅电压漂移的测量 ,证明了均匀 FN应力老化后栅氧化层中陷阱呈非均匀分布 .不同厚度的栅氧化层产生 SIL C的机制不尽相同 ,薄栅以陷阱辅助隧穿为主 ,类 Pool- Frankel机制在厚二氧化硅栅中起主导作用 .     

漏雪崩应力下热载流子注入引起的MOSFET退变特性研究

本文对亚微米MOSFET在漏雪崩恒流应力(DAS)条件下热载流子注入引起的退变现象做了实验研究。实验结果表明:在一般的恒流应力条件下,栅氧化层中由空穴注入形成的空穴陷阱电荷对器件特性起主要影响作用。恒流应力过程中,任何附加的电子注入都可使器件退变特性发生明显变化,实验结果还证实,漏雪崩应力期间形成的空穴陷阱电荷可明显降低器件栅氧化层的介质击穿特性。     

集成运算放大器参数时漂的1／f噪声预测方法

寿命试验和噪声测试结果表明，如果集成运算放大器的主要失效模式是输入偏置电流或失调电流随时间的漂移，则这种漂移量与运放的１／ｆ噪声电流具有强相关性，二者近似呈正比关系。理论分析表明，这种漂移可因于作为１／ｆ噪声直接起源的氧化层陷阱对硅中电子的慢俘获作用。     

Effect of composition on deep levels in heteroepitaxial GexSi1−x layers and evidence for dominant intrinsic recombination-Generation in relaxed ge layers on Si

Electron traps, hole traps, and the dominant recombination-generation (R-G) centers have been investigated with deep level transient spectroscopy and current-voltage/temperature measurements in heteroepitaxial Ge_xSi_1-x alloys with x ranging from 0.15 to 1, grown on graded Ge_y.Si_1−y/Si substrates. For all samples with compositions x < 0.85, which retain the Si-like conduction band structure, we detect a dominant electron trap and R-G center whose activation energy is ΔE = 0.5 eV, independent of composition. This energy agrees with that of electron traps previously reported for plastically deformed (PD) Si, suggesting a connection to the Si-like band structure. This 0.5 eV level dominates the reverse leakage current over a wide range of growth and annealing conditions for the 30% Ge samples, indicating that the electronic state at ΔE = 0.5 eV is a very efficient R-G center, as would be expected from its midgap position. Alternatively, for strain relaxed, pure Ge (< 1), we detect electron traps at E_c − 0.42 eV and E_c − 0.28 eV, in agreement with the literature on PD Ge and Ge bicrystals. These energies are significantly different from those observed for x < 0.85, and we conclude that these changes in activation energy are due to changes in the conduction band structure for high Ge content. Moreover, in contrast with the Si-like samples (x < 0.85), the reverse leakage current in the relaxed Ge cap layer is not controlled by deep levels, but is rather dictated by intrinsic, band-to-band generation due to the reduced bandgap of Ge as compared to Si-like alloys. Only for reverse bias magnitudes which incorporate a significant portion of the graded buffer within the depletion region do R-G centers dominate the reverse leakage current. These results confirm the high quality of the strain-relaxed, pure Ge cap region which was grown on a Ge_ySi_1−y/Si step graded heterostructure (where y was increased from 0 to 1) by ultra high vacuum chemical vapor deposition. Finally, we report for the first time, what is apparently the dislocation kink site state at E_c − 0.37 eV, in a Ge_xSi_1−x alloy.     

电应力对GaAlAs红外发光二极管低频噪声的影响

在宽范围偏置条件下,测量了电应力前后GaAlAs红外发光二极管（IRED）的低频噪声,发现应力前后1／f噪声随偏置电流变化的规律没有改变,但应力后1／f噪声幅值比应力前增加大约i00倍。基于载流子数和迁移率涨落的理论分析表明,GaAlAs IRED的1／f噪声在小电流时反映体陷阱特征,大电流时反映激活区陷阱特征,1／f噪声的增加归因于电应力在器件有源区诱生的界面陷阱和表面陷阱,因而,1／f噪声可以用来探测电应力对该类器件有源区的潜在损伤。     

Thermally stimulated current in SiO2

Thermally stimulated current (TSC) techniques provide information about oxide-trap charge densities and energy distributions in MOS (metal-oxide-semiconductor) capacitors exposed to ionizing radiation or high-field stress that is difficult or impossible to obtain via standard capacitance–voltage or current–voltage techniques. The precision and reproducibility of measurements through repeated irradiation/TSC cycles on a single capacitor is demonstrated with a radiation-hardened oxide, and small sample-to-sample variations are observed. A small increase in E′_δ center density may occur in some non-radiation-hardened oxides during repeated irradiation/TSC measurement cycles. The importance of choosing an appropriate bias to obtain accurate measurements of trapped charge densities and energy distributions is emphasized. A 10 nm deposited oxide with no subsequent annealing above 400°C shows a different trapped-hole energy distribution than thermally grown oxides, but a similar distribution to thermal oxides is found for deposited oxides annealed at higher temperatures. Charge neutralization during switched-bias irradiation is found to occur both because of hole-electron annihilation and increased electron trapping in the near-interfacial SiO₂. Limitations in applying TSC to oxides thinner than 5 nm are discussed.     

Digital deep level transient spectroscopy considered for discrimination of traps closely spaced in emission coefficients in semiconductors

A method is presented for analysis of digitally recorded capacitance transients to give activation energies and capture cross-sections of two deep levels which would yield overlapping peaks in conventional DLTS spectra. It is shown that baseline errors can be overcome by proper analysis of the data. The accuracy of the method is examined by simulation with parameters representative of a typical DLTS system. The addition of various noise levels is also simulated and the effects of averaging of transients on the ability to discriminate closely spaced traps is examined quantitatively.     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

First Evidence of Electron Trapped Ln2+ Promoting Afterglow on Eu2+, Ln3+ Activated Persistent Phosphor-Example of BaZrSi3O9:Eu2+, Sm3+

BaZrSi₃O₉:Eu²⁺, Sm³⁺ (Em:525 nm) is prepared. The role played by the trivalent co-doping ion Sm³⁺ in the afterglow and the type of trap are clarified. BaZrSi₃O₉:Eu²⁺, Sm³⁺ is found to produce Sm²⁺ during the excitation by X-ray absorption near-edge structure (XANES), etc., and it is thus proved that Sm³⁺ exists as an electron trap in the afterglow process. In the field of persistent phosphors activated by Eu²⁺ and Re³⁺ such as Sm³⁺ or Dy³⁺ having been widely utilized as emergency guide lights, clock faces, etc. for > 25 years, for the first time it is successfully observed that after excitation Re²⁺ is formed, transferring its electron to 5d band of Eu²⁺, returning to Re³⁺ by itself, where the decrease in Sm²⁺ coincides with the increase in Sm³⁺, and the two decay time τ₁ and τ₂ of PL (⁵D₀→⁷F₀) of Sm²⁺ coincides with the two evolution time of PL (5d→4f) of Eu²⁺. The behavior of electron transfer from Sm²⁺ to Eu²⁺ as a key of afterglow is detected. The detailed afterglow mechanism is proposed by analysis of thermoluminescence and defect reaction, which is very important for the in-depth investigation of the long afterglow material and the further improvement of the mechanism.     

Electrical properties of silicon dioxide films fabricated at 700°C. II: Low pressure hydride deposition

We have investigated the effects of different annealing treatments on silicon dioxide films produced from the reaction of dichlorosilane and nitrous oxide at 700° C. The electrical quality of these LPCVD films was evaluated by measuring oxide charge and interface trap densities on metal oxide semiconductor (MOS) capacitors. These densities were measured before and after avalanche injection of electron currents into the oxide films. The results of these studies were as follows. (1) The LPCVD oxide films required a post deposition anneal at 1000° C to produce as-grown charge densities similar to those of a standarddry thermal oxide grown and annealed at 1000° C. (2) Post-injection charge densities of LPCVD films given a post deposition anneal at 1000°C were an order of magnitude greater than those of the standard dry thermal oxide. (3) Different annealing treatments produced a series of dominant electron trapping centers in the oxide bulk₁₇ with capture cross sections ranging from 10⁻¹⁴ cm² to 10⁻¹⁷ cm². (4) The electron traps in the LPCVD oxides films were similar to those previously observed in standardwet thermal oxides grown and annealed above 1000° C.     

利用MOSFET亚阈I-V特性进行辐射感生界面陷阱的测量

本文利用MOSFET亚阈IV曲线对加固和非加固MOSFET的辐射感生界面陷阱密度进行了测量.分析和讨论了辐射感生的界面陷阱密度依赖于辐射总剂量和辐射剂量率的变化关系     

Electrical properties of undoped bulk ZnO substrates

Undoped bulk ZnO crystals obtained from Tokyo Denpa show either resistive behavior [(5×10⁴)−(3×10⁵) Ohm cm) or low n-type conductivity (n ⋍10¹⁴ cm⁻³) with mobilities in the latter case of 130–150 cm²/V sec. The variation in resistivity may be related to the thermal instability of Li that is present in the samples. The Fermi level is pinned by 90-meV shallow donors that are deeper than the 70 meV and hydrogen-related 35-meV shallow donors in Eagle Pitcher and Cermet substrates. In all three cases, 0.3-eV electron traps are very prominent, and in the Tokyo Denpa material they dominate the high-temperature capacitance-frequency characteristics. The concentration of these traps, on the order of 2×10¹⁵ cm⁻³, is about 20 times higher in the Tokyo Denpa ZnO compared to the two other materials. The other electron traps at E_c −0.2 eV commonly observed in undoped n-ZnO are not detected in conducting Tokyo Denpa ZnO samples, but they may be traps that pin the Fermi level in the more compensated high-resistivity samples.     

Numerical Analysis of Characterized Back Interface Traps of SOI Devices by R-G Current

Characterized back interface traps of SOI devices by the Recombination-Generation (R-G) curren: has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSiS-ISE. The basis of the principle for the R-G current's characterizing the back interface traps of SOI lateral p+p-n+ diode has been demonstrated. The dependence of R-G cur rent on interface trap characteristics has been examined, such as the state density, surface recombination velocity and the trap energy level. The R-G current proves to be an effective tool for monitoring the back interface of SOI devices.